Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2005-05-19
2009-08-04
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
With measuring or testing
C438S057000, C438S694000, C438S717000, C438S763000, C438S780000, C257SE21577
Reexamination Certificate
active
07569403
ABSTRACT:
A pattern evaluation method using a circuit arrangement provided with N (N is a natural number of 2 or greater) circuit groups having wiring whose widths are different to each other, each circuit group including first to Mth circuits having first to Mth (M is a natural number of 2 or greater) wiring formed of a conductive layer, respectively, each of the first to the Mth wiring having the same width that is electrically measurable, the pattern evaluation method includes:arranging patterns to be evaluated so that the Mth wiring or a layer in the vicinity thereof is locally removed;electrically calculating a first characteristic value indicating a characteristic of the first circuit including at least the wiring width of the first wiring;electrically calculating an Mth characteristic value which is a value indicating the characteristic of the Mth circuit and dependent on a geometric relationship between the pattern to be evaluated and the Mth wiring; andevaluating the characteristic of the pattern to be evaluated based on the first characteristic value to the Mth characteristic value obtained for at least two circuit groups of the N circuit groups.
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Notification of Reason for Rejection issued by the Japanese Patent Office on May 23, 2008, for Japanese Patent Application No. 2004-150386, and English-language translation thereof.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Kyoung
Richards N Drew
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