Pattern detection and synchronization circuit

Pulse or digital communications – Spread spectrum – Direct sequence

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375119, 3701054, H04L 700

Patent

active

052971856

ABSTRACT:
For identifying a preamble or other pattern in a binary bit stream, containing data coded to have a different average number of ones to zeroes from the pattern in question, a pattern detection circuit includes a shift register, a unitary adder and a comparison circuit. The shift register has a sufficient length that there is at least a high probability that the number of ones stored therein is different for the pattern in question from the range of number of ones found in that length of the data stream. The unitary adder counts the number of ones in the register, and this value is compared with the range of values which that length of the pattern should contain. If the pattern to be detected is a preamble used for bit synchronization, and the data are coded in a way which may lead to possibility of synchronization to a subharmonic, a ones-average detector may be used to disable the synchronization circuit for a local clock until the preamble is detected. For modest length preambles, there still should be sufficient length to synchronize the clock after preamble detection.

REFERENCES:
patent: 4231071 (1980-10-01), Anderson
patent: 4675652 (1987-06-01), Machado
patent: 4847877 (1989-07-01), Besseyre
QIC Development Standard-1350 Revision E 17 Jan. '90.
IEEE Transactions of Magnetics, vol. MAG-20, No. 5, Sep. 1984, "Monte--Carlo Analysis of Recording Codes" by Paul K. Davis, p. 887.
IBM J. Res. Develop, vol. 33, No. 1, Jan. 1989, "Statistical Properties of Selected Recording Codes", by Thomas D. Howell, pp. 60-73.

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