Pattern based dynamic drive current balancing for data...

Details Pattern based dynamic drive current balancing for data... Pattern based dynamic drive current balancing for data...

2003-03-20

2004-12-14

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

Reexamination Certificate

active

06831487

ABSTRACT:

BACKGROUND OF INVENTION
As shown in
FIG. 1
, a typical computer system
10
has, among other components, a microprocessor
12
, one or more forms of memory
14
, integrated circuits
16
having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths
18
, e.g., wires, buses, etc., to accomplish the various tasks of the computer system
10
.
When an integrated circuit (
16
in
FIG. 1
) communicates with another integrated circuit, i.e., “chip-to-chip communication,” data is transmitted in a series of binary 0's and 1's from a transmitting circuit to a receiving circuit. Accordingly, at any particular time, a data signal received at the receiving circuit may have a low voltage potential representative of a binary ‘0 ’ or a high voltage potential representative of a binary ‘1.’
FIG. 2
shows a portion of a typical transmission system
20
. The transmission system
20
includes a transmitting circuit
22
, a data channel (also known as a “board trace”)
24
, and a receiving circuit
26
. Generally, circuit-to-circuit wireline communication occurs by one circuit transmitting data and another circuit receiving the data over wires implemented on a computer board on which the sending and receiving circuits are disposed. As shown in
FIG. 2
, the transmitting circuit
22
drives data into the data channel
24
using the a driver stage
28
formed by a first driver
30
and a second driver
32
. The receiving circuit
26
receives the data at the other end of the data channel
24
using some receiving device
34
.
As mentioned above, in data signaling, a data bit is driven into the data channel
24
using specific voltage levels, i.e., logic high and logic low. In binary transmission, in which data is coded as a series of 1's and 0's, a ‘1’ could be represented by any voltage above a particular value and a ‘0’ could be represented by any voltage below a particular value.
FIG. 3
shows a schematic of the driver stage
28
shown in FIG.
2
. The first driver
30
is formed using a pull-up device
36
and a pull-down device
38
, and the second driver
32
is formed using a pull-up device
40
and a pull-down device
42
. Those skilled in the art will understand that the inputs to the driver
30
and the second driver
32
are controlled separately in order to control, among other things, crow bar currents and voltage swing levels on the data channel
24
. When activated, each of the pull-up and pull-down devices
36
,
38
,
40
, and
42
effectively form a resistance, and when deactivated, each of the pull-up and pull-down devices
36
,
38
,
40
, and
42
form an open circuit, or +infinite resistance.
FIG. 4
shows different states of the driver stage
28
. When the driver stage
28
drives a ‘1,’ the pull-up devices
36
and
40
of the first and second drivers
30
and
32
, respectively, are switched ‘on,’ or otherwise activated, and the pull-down devices
38
and
42
of the first and second drivers
30
and
32
, respectively, are switched ‘off,’ or otherwise deactivated. This arrangement of the pull-up and pull-down devices
36
,
38
,
40
, and
42
causes the driver stage
28
to pull up the voltage value on the data channel
24
.
Alternatively, when the driver stage
28
drives a ‘0,’ the pull-down devices
38
and
42
of the first and second drivers
30
and
32
, respectively, are switched ‘on,’ or otherwise activated, and the pull-up devices
36
and
40
of the first and second drivers
30
and
32
, respectively, are switched ‘off,’ or otherwise deactivated. This arrangement of the pull-up and pull-down devices
36
,
38
,
40
, and
42
causes the driver stage
28
to pull down the voltage value on the data channel
24
.
As discussed with reference to
FIG. 4
, the driver stage
28
, when driving a ‘1,’ places a voltage step on the data channel
24
. However, because the data channel
24
is typically lossy at high frequencies, the voltage step generated by the driver stage
28
suffers skin effect and dielectric loss. Losses in long data channels do not only introduce attenuation of data signal integrity, but more significantly, cause signal distortion. Such distortion results in intersymbol interference (ISI), which is described below.
A significant factor in achieving the highest possible data rate relates to the signal to noise ratio present at the receiving circuit. The noise present at the receiving circuit includes noise introduced by the data channel and noise attributable to interference from preceding bits of data. Such interference is ISI. ISI is a distortion in the received signal resulting from the temporal spreading and consequent overlap of individual signal pulses and to the degree that the receiving circuit cannot reliably distinguish between changes of state. It follows that at a certain threshold, intersymbol interference compromises the integrity of the data signal at the receiving circuit.
All of the effects discussed above that result from signal attenuation along the data channel leads to data jitter, which means that data does not reach a receiving circuit at the same time with respect to a clock signal for every data bit sent. This leads to uncertainty in data capture at the receiving circuit. Moreover, when a series of 1's or 0's are transmitted over a long data channel, jitter is amplified because the voltage swing at the receiving circuit increases or decreases depending on the number of consecutive 1's or 0's transmitted.
To this end,
FIG. 5
shows a behavior of a data signal
50
in the transmission system
20
shown in FIG.
2
and using a driver stage
28
as described with reference to
FIGS. 3 and 4
. In the bit sequence shown in
FIG. 5
, the transmittal of the first four bits, ‘0101,’ to the data channel (
24
in
FIGS. 2
,
3
, and
4
) from the driver stage (
28
in
FIGS. 2
,
3
, and
4
) occurs by switching the state of the driver stage (
28
in
FIGS. 2
,
3
, and
4
) between the ‘0’ arrangement and ‘1’ arrangement shown in FIG.
4
. The next several bits transmitted by the driver stage (
28
in
FIGS. 2
,
3
, and
4
) are 0's, and thus, the driver stage (
28
in
FIGS. 2
,
3
, and
4
) remains in the ‘0’ arrangement shown in
FIG. 4
for some amount of time.
As shown in
FIG. 5
, as the driver stage (
28
in
FIGS. 2
,
3
, and
4
) remains in the ‘0’ arrangement shown in
FIG. 4
, the data signal
50
drifts to a voltage value below the ‘0’ threshold. Then, when the driver stage (
28
in
FIGS. 2
,
3
, and
4
) is again required to transmit a ‘1,’ the voltage step driven onto the data channel (
24
in
FIGS. 2
,
3
, and
4
) by the driver stage (
28
in
FIGS. 2
,
3
, and
4
) results in the data signal
50
reaching a voltage value less than that reached previously when driving a ‘1.’ Accordingly, as discussed above, such signal attenuation leads to ISI and increased data jitter.
FIG. 6
shows a behavior of a data signal
51
in the transmission system
20
shown in FIG.
2
and using a driver stage
28
as described with reference to
FIGS. 3 and 4
. In the bit sequence shown in
FIG. 6
, the transmittal of the first four bits, ‘0101,’ to the data channel (
24
in
FIGS. 2
,
3
, and
4
) from the driver stage (
28
in
FIGS. 2
,
3
, and
4
) occurs by switching the state of the driver stage (
28
in
FIGS. 2
,
3
, and
4
) between the ‘0’ arrangement and ‘1’ arrangement shown in FIG.
4
. The next several bits transmitted by the driver stage (
28
in
FIGS. 2
,
3
, and
4
) are 1's, and thus, the driver stage (
28
in
FIGS. 2
,
3
, and
4
) remains in the ‘1’ arrangement shown in
FIG. 4
for some amount of time.
As shown in
FIG. 6
, as the driver stage (
28
in
FIGS. 2
,
3
, and
4
) remains in the ‘1’ arrangement shown in
FIG. 4
, the data signal
51
drifts to a voltage value above the ‘1’ threshold. Then, when the driver stage (
28
in
FIGS. 2
,
3
, and
4
) is again required to transmit a ‘0,’ the voltage drop

Affiliated with

Also associated with

Rating

Pattern based dynamic drive current balancing for data... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pattern based dynamic drive current balancing for data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern based dynamic drive current balancing for data... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3273017