Multiplex communications – Wide area network – Packet switching
Patent
1995-05-31
1996-10-29
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
3701101, H04J 326, H04Q 139
Patent
active
055703712
ABSTRACT:
A J1 byte processing circuit is provided with a J1 byte latch pulse sampling circuit, which samples in preset periods a J1 byte latch pulse. The sampling circuit generates, in accordance with the sampled J1 byte latch pulse, a data acquisition request to instruct acquisition of a J1 byte from the path overhead of an SPE level signal of STS-1 with the J1 byte latch pulse sampled by the sampling circuit, and sends it to a microcomputer interface. The microcomputer acquires into it the J1 byte from the J1 latching section in accordance with the data acquisition request. This configuration reduces the processing load on the microcomputer, and thereby enables the microcomputer to execute other processes even during the collection of J1 bytes.
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NEC Corporation
Olms Douglas W.
Phillips Matthew
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