Path searched device and CDMA receiver with the same

Details Path searched device and CDMA receiver with the same Path searched device and CDMA receiver with the same

1999-08-20

2002-11-26

Urban, Edward F. (Department: 2685)

Multiplex communications

Communication over free space

Combining or distributing information via code word channels...

C370S335000, C370S350000, C375S145000, C375S355000

Reexamination Certificate

active

06487193

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a path searching device for a direct sequence CDMA (Code Division Multiple Access) communication system and to a CDMA receiver employing the path searching device.
A CDMA receiver for the direct sequence CDMA communication system includes a path searching device (or a path searcher) for finding despread timing. Although the path searching device can be a sliding correlator, it is usually a matched filter. However, it would be desirable to reduce the circuit scale of these devices.
FIG. 5
shows a CDMA receiver. Reference numeral
101
designates an antenna,
102
a reception demodulator,
103
an AD converter,
104
a searcher (a path search device),
105
a despreading unit, and
106
a determination unit. Although the searcher
104
may be a matched filter or a sliding correlator, it is usually a matched filter. The despreading unit
105
has a code generator for despreading.
The antenna
101
is either installed in a base station or a mobile station of a direct sequence CDMA communication system. The antenna
101
receives a spread and modulated signal. The reception demodulator
102
demodulates the signal, the AD converter
103
converts the signal into a digital signal, the despreading unit
105
despreads the digital signal, and the determination unit
106
reproduces a received bit string. In order to synchronously generate spreading codes for a despreading operation carried out by the despreading unit
105
, the searcher
104
provides a timing signal.
FIG. 6
shows a prior art searcher. Numerals
111
1
-
111
n
designate delay elements (DLs) that form a shift register,
112
1
-
112
n+1
multipliers,
113
an adder,
114
a memory, and
115
a controller. The delay elements
111
1
-
111
n
serve as a shift register, while the multipliers
112
1
-
112
n+1
, and adder
113
constitute a matched filter.
If the AD converter
103
of
FIG. 5
carries out a sampling operation according to a particular chip rate, the delay elements
111
1
-
111
n
of
FIG. 6
serves as a shift register that provides a time delay based on the chip rate. In order to carry out oversampling that is several times faster than the chip rate, the delay elements provide a time delay corresponding to an oversampling interval. In this case, the number of the delay elements must comply with a multiple related to the oversampling.
The shift register made of the delay elements
111
1
-
111
n
receives an input signal “in” which is a digital signal sampled and converted by the AD converter
103
. Output signals from the taps of the delay elements are multiplied in the multipliers
112
1
-
112
n+1
by spreading codes cd
1
-cd
n+1
provided by a code generator (not shown). Further, output signals from the multipliers are then combined in the adder
113
.
An output signal from the adder
113
represents correlation values between spreading codes of the spread and modulated signal, and spreading codes for despreading. An average of the correlation values from the adder
113
is obtained with the use of the memory
114
, and according to the average, the controller
115
provides a timing signal to the despreading unit
105
. According to the timing signal, the despreading unit
105
controls the timing of the code generator (not shown) for generating spreading codes.
The shift register that forms the matched filter of the searcher
104
for a CDMA receiver must have a number of stages that is sufficient to cover the length of spreading codes. In order to enable oversampling, the shift register must have taps whose number corresponds to an oversampling multiple. In particular, the number of stages of the shift register must be equal to the product of the length of spreading codes and the oversampling multiple. This raises a problem since circuit scale of the matched filter is greatly increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a path searching device that has a reduced circuit scale.
Another object of the present invention is to provide a path searching device that operates to execute a reduced number of processes.
These and other objects are met by a path searching device according to the present invention that determines despreading timing in a direct sequence CDMA communication system.
FIG. 1
shows the searching device which includes a sampling unit that samples an input signal by low-speed oversampling based on an integer multiple of a chip rate and by high-speed oversampling that is faster than the low-speed oversampling. A first circuit of a matched filter structure is included that finds a correlation value between a spreading code and a signal provided by the low-speed oversampling. Further, the first circuit finds timing corresponding to a maximum correlation value. A second circuit
17
is also included that finds despreading timing according to correlation values between a signal provided by the high-speed oversampling and spreading codes generated according to the timing provided by the first circuit.
The second circuit of the path search device receives a spreading code generated according to the timing provided by the first circuit. The second circuit also shifts the phase of the spreading code by an interval of the high-speed oversampling and, finds a correlative value between the spreading code and a signal provided by the high-speed oversampling. Further, the second circuit integrates such correlation values and finds a despreading timing according to a phase that provides a maximum integrated value.
The second circuit of the path search device consists of a delay element for receiving a spreading code generated according to the timing provided by the first circuit and shifting the phase of the spreading code by an interval of the high-speed oversampling. A multiplier is also included that finds a correlation value between the spreading code passed through the delay element and a signal provided by the high-speed oversampling. An adder and a delay element that integrates an output signal of the multiplier, and a timing signal output unit that finds despread timing according to a maximum value found in the integrated output signal.
The second circuit of the path search device according to the present invention may also consist of a matched filter that receives approximately one chip length of a signal provided by the high-speed oversampling and finds a correlative value accordingly.
The path search device according to the present invention may also consist of a matched filter serving as the first and second circuits. A switch is also included that switches a signal provided by the high-speed oversampling and a signal provided by the low-speed oversampling from one to another in time division so that the signals are supplied to the matched filter in time division. An arrangement is further providing despreading timing when the high-speed oversampling provides a signal.
The present invention also consists of a CDMA receiver having a reception demodulator, an AD converter, a despreading unit, a determination unit, and a path search device. The path searching device can consist of a sampling unit for sampling an input signal by low-speed oversampling based on an integer multiple of a chip rate and by high-speed oversampling that is faster than the low-speed oversampling. A first circuit of a matched filter structure for finding a correlative value between a spreading code and a signal provided by the low-speed oversampling, further, finding timing corresponding to a maximum correlative value. A second circuit is also included for finding despreading timing according to correlative values between a signal provided by the high-speed oversampling and spreading codes generated according to the timing provided by the first circuit.


REFERENCES:
patent: 5881058 (1999-03-01), Chen
patent: 5949812 (1999-09-01), Turney et al.
patent: 6064690 (2000-05-01), Zhou et al.
patent: 6144649 (2000-11-01), Storm et al.
patent: 6226315 (2001-05-01), Sriram et al.

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