Path delay allocation method in the physical hierarchy

Details Path delay allocation method in the physical hierarchy Path delay allocation method in the physical hierarchy

1992-11-23

1995-09-19

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054522285

ABSTRACT:
An electronic apparatus of hierarchical design includes a path extending between a plurality of hierarchy levels. Path delays at the upper hierarchy level are calculated beforehand, and path delay target times at subdivided paths of the path extending between the upper and lower hierarchy levels are determined by proportional distribution of the calculated path delay. The path delay target times can also be determined for an open path and a through path in the physical hierarchy, so that, when the path delay target time requirement is obeyed in the physical hierarchy, the path delays in the entire apparatus can be limited to less than their target times.

REFERENCES:
patent: 5010493 (1991-04-01), Matsumoto et al.
patent: 5062067 (1991-10-01), Schaefer et al.
patent: 5068812 (1991-11-01), Schaefer et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5109168 (1992-04-01), Rusu
patent: 5235521 (1993-08-01), Johnson et al.
Nair, Ravi et al. "Generation of Performance Constraints for Layout," IEEE Transactions on Computer-Aided Design, vol. 8, No. 8, Aug. 1989, pp. 860-874. (in English).

Affiliated with

Also associated with

Rating

Path delay allocation method in the physical hierarchy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Path delay allocation method in the physical hierarchy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Path delay allocation method in the physical hierarchy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1833711