Patching methods and apparatus for fabricating memory modules

Details Patching methods and apparatus for fabricating memory modules Patching methods and apparatus for fabricating memory modules

2006-06-13

2006-06-13

Geyer, Scott (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S017000, C365S201000

Reexamination Certificate

active

07060512

ABSTRACT:
A method and apparatus for building a memory module using improved patching schemes comprises, mounting multiple primary and secondary memory parts on a multi-layer circuit board, positioning I/O bit line patching networks adjacent to the primary and secondary memory parts, matching read/write control signals for primary and secondary memory parts which share I/O bit line patching networks, testing primary and secondary memory parts to identify non-operable I/O lines, and patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part. The method and apparatus include multi-layer circuit boards which utilize 2-to-1, 4-to-1, and 8-to-1 patching configurations.

REFERENCES:
patent: 5644541 (1997-07-01), Siu et al.
patent: 5987623 (1999-11-01), Ushida
patent: 6057169 (2000-05-01), Singh et al.

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