Passive semiconductor device mounted as daughter chip on...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S528000, C257S758000, C438S957000, C438S329000, C438S118000, C438S622000

Reexamination Certificate

active

06504227

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-185119, filed Jun. 30, 1999; and No. 2000-189937, filed Jun. 23, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit device, its manufacturing method, a circuit board and a method of manufacturing the same.
A monolithic IC having an active element such as a transistor and a passive element such as a resistor, a capacitor or an inductor integrated on a semiconductor substrate is low in manufacturing cost, permits suppressing the power consumption, and can be miniaturized, and thus, the monolithic IC can be formed as a one chip.
However, where an inductor is formed on a semiconductor substrate, a parasitic capacitance and a parasitic resistance (eddy current loss) are generated between the conductor forming the inductor and the semiconductor substrate. Therefore, in order to obtain an inductor having a high Q factor, it is necessary to lower the parasitic capacitance and the parasitic resistance.
As a method for lowering the parasitic capacitance and the parasitic resistance, proposed is a method of forming an inductor above a groove formed on the surface of a semiconductor substrate. To be more specific, it is proposed in, for example, U.S. Pat. No. 5,539,241, that an inductor is formed in an air-floating wiring structure so as to increase the distance between the inductor and the semiconductor substrate and, thus, to lower the parasitic capacitance and the parasitic resistance.
In the conventional structure exemplified above, however, it was impossible to ensure a sufficient mechanical strength because the inductor is floating in the air.
It is also proposed to form an active element such as a transistor and a passive element such as a capacitor or an inductor on different substrates, followed by bonding these elements by using a bump, as disclosed in, for example, ISSCC98/SESSION 16, DIGEST OF TECHNICAL PAPERS, pp 248-249.
However, the substrate having an active element formed thereon and the substrate having a passive element formed thereon are arranged such that the element-forming surfaces are allowed to face each other. It follows that the semiconductor substrate having, for example, a transistor formed thereon is apart from the inductor by only a distance determined by the bump. As a result, it was difficult to lower sufficiently the influence of the semiconductor substrate having the transistor formed thereon.
Also, a circuit board having a conductive connecting portion formed within an insulating layer is known to the art. In the conventional technology, however, it is difficult to control the shape of the conductive connecting portion, and the step for forming the conductive connecting portion is made complex.
BRIEF SUMMARY OF THE INVENTION
A first object of the present invention is to provide an integrated circuit device having an active element and a passive element formed on a single semiconductor substrate, in which the parasitic capacitance and the parasitic resistance can be lowered sufficiently and a sufficient mechanical strength can be obtained, and a method of manufacturing the particular integrated circuit device.
A second object of the present invention is to provide an integrated circuit device prepared by connecting by a suitable means a semiconductor substrate having an active element formed thereon and another substrate having a passive element formed thereon, in which the influence of the semiconductor substrate can be sufficiently lowered, and a method of manufacturing the particular integrated circuit device.
Further, a third object of the present invention is to provide a circuit board having a conductive connecting portion extending through an insulating layer, in which the shape of the conductive connecting portion can be controlled easily or the process for forming the conductive connecting portion can be simplified, and a method of manufacturing the particular circuit board.
According to a first aspect of the present invention, there is provided an integrated circuit device, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region.
According to a second aspect of the present invention, there is provided a method of manufacturing an integrated circuit device, comprising forming a groove having a depth of at least 20 &mgr;m on the side of one main surface of a semiconductor substrate; forming an active element on the side of the main surface of the semiconductor substrate; burying an insulating material in the groove to form an insulating region; and forming a passive element directly or indirectly on the insulating region.
In each of the first and second aspects of the present invention, it is desirable for the passive element to be an inductor, particularly, a spiral inductor. It is desirable for the conductive material forming the inductor to contain as a main component Cu, Au, Ag or Al.
According to the first and second aspects of the present invention, an insulating material is buried in a groove having a depth of at least 20 &mgr;m formed on the side of the main surface of the semiconductor substrate, and a passive element is formed directly or indirectly on the insulating region formed by burying the insulating material. It follows that it is possible to lower sufficiently the parasitic capacitance and the parasitic resistance and to ensure a sufficient mechanical strength.
In the first and second aspects of the present invention, it is desirable to form the groove by an anisotropic etching. It is desirable for the anisotropic etching to be performed by a reactive ion etching, particularly, a high density plasma etching, using a gas containing fluorine. In the present invention, formed is a groove having a depth of at least 20 &mgr;m. By employing the anisotropic etching, it is possible to form a groove having a side wall substantially perpendicular to the substrate. Therefore, even in the case of forming a deep groove having a depth of at least 20 &mgr;m, the area of the groove-forming region can be diminished to a minimum level. Also, since a deep groove having a depth. of at least 20 &mgr;m is formed, it is desirable for the anisotropic etching rate to be higher than the ordinary etching rate. In the present invention, the etching can be performed at a high etching rate because a reactive ion etching is performed by using a fluorine-containing gas.
In the present invention, it is desirable for the insulating region to be formed by pouring an insulating fluid into the groove, followed by solidifying the insulating fluid. Since a deep groove having a depth of at least 20 &mgr;m is formed in the present invention, a long time is required for forming the insulating material if the insulating material is formed by a deposition method. The insulating material can be formed efficiently by burying an insulating fluid in the groove, followed by solidifying the insulating fluid, i.e., by using a coated film.
In the first and second aspects of the present invention, it is desirable for the groove to be formed after formation of the active element. In general, a high temperature of about 1,000° C. is required for forming the active element. Where the active element is formed in advance before formation of the groove, it is possible to use an insulating film, e.g., an organic coated film, having a low resistance to heat as an insulating material buried in the groove so as to form the insulating material efficiently.
According to a third aspect of the present invention, there is provided an integrated circuit device, comprising a first substrate consisting of a semiconductor su

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Passive semiconductor device mounted as daughter chip on... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Passive semiconductor device mounted as daughter chip on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Passive semiconductor device mounted as daughter chip on... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3065657

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.