Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-03-28
2001-11-06
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S091000, C327S337000, C327S554000
Reexamination Certificate
active
06313668
ABSTRACT:
BACKGROUND OF THE INVENTION
Each capacitor in a switched capacitor circuit can be described as acting either as a capacitor or as a resistor. A capacitor in a switched capacitor circuit is said to act as a capacitor when the capacitor has memory of a previous value, and passes current that is proportional to dv/dt (i.e., I (current)=Cdv/dt). Such a capacitor generally performs some type of frequency shaping because the capacitor passes more and more current as the frequency of the voltage increases across the terminals of the capacitor. In contrast, a capacitor in a switched capacitor circuit is said to act as a resistor when the capacitor has no memory of a previous value, and passes current that is proportional to a voltage (i.e., V=iR (voltage=current*resistance), or equivalently I=CV/T (wherein T is the period of a sampling clock)).
Unlike with a capacitor, the value of the current passed by a true resistor is independent of the frequency of the input signal.
FIG. 1
illustrates a circuit
20
wherein the capacitor
22
therein is said to act as a capacitor—i.e., the capacitor passes more current as the frequency of the input signal, V
in
, increases. Hence, the current (i) provided to the capacitor is equal to C*dv/dt. In contrast,
FIG. 2
illustrates a circuit
30
wherein the capacitor
32
therein is said to act as a resistor—i.e., the capacitor passes a current proportional to the magnitude of the input signal, V
in
. Hence, the current (i) provided to the capacitor is equal to CV/T. In
FIG. 2
, the waveforms of two non-overlapping clock signals, clk
1
and clk
2
, are depicted under the circuit
30
. While clock signal clk
1
controls switch
1
in the circuit, clock signal clk
2
controls switch
2
.
It is generally advantageous in discrete time frequency shaping circuits to use circuits that have minimal attenuation and provide feedthrough isolation between samples (wherein v
out
is not directly coupled to v
in
).
FIG. 3
illustrates a typical continuous-time analogous circuit
40
wherein the circuit
40
includes a feedthrough isolation sample and hold portion
42
in front. A corresponding discrete-time analogous circuit
50
is illustrated in
FIG. 4
, and is provided by replacing each resistor shown in
FIG. 3
with a capacitor and providing switches that move i=CV/T. In
FIG. 4
, the capacitor C
shape
still acts as a capacitor, and passes current that is proportional to dv/dt (i.e., i (current)=Cdv/dt).
FIG. 4
also illustrates the structure of the sample and hold portion of the circuit. As shown, while the resistive-type capacitors, C
g
and C
f
, in the zero portion already have direct feedthrough isolation, capacitor C
shape
does not have direct feedthrough isolation without the sample and hold circuit in front. Adding a switch in front of capacitor C
shape
(instead of providing the sample and hold portion) will not provide direct feedthrough isolation because when the switch is closed, v
in
will directly change v
out
.
FIG. 4
illustrates the traditional method of implementing the required sample and hold function. As shown, two active stages are implemented (the sample and hold portion and the zero portion), and each requires a large area, power-consuming operational amplifier. However, it is advantageous to limit the area of a circuit as well as limit the power consumed by a circuit. For example, with regard to Ethernet chips, as the number of required ports (i.e., channels) continue to increase, package power dissipation is becoming more and more of a critical issue. Cutting power consumption, such as in half, for a stage in a circuit is significant because more ports (i.e., channels) can be added to the same chip while maintaining safe die temperatures.
OBJECTS AND SUMMARY
It is an object of an embodiment of the present invention to provide a switched capacitor circuit that is configured to perform a sample and hold with frequency shaping operation while consuming less power.
It is a further object of an embodiment of the present invention to provide a switched capacitor circuit that is configured to perform a sample and hold with frequency shaping operation, and consumes less area.
It is a further object of an embodiment of the present invention to provide a switched capacitor circuit that includes passive elements configured to perform a sample and hold operation.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a passive sample and hold for an active switched capacitor circuit that employs frequency shaping. The sample and hold does not require a pair of large area, power-consuming operational amplifiers and, as such, consumes less power and less area than conventional sample and hold circuits.
Preferably, the sample and hold is operable in four different states wherein a different set of switches are closed in each of the four states. Preferably, the switches are controlled by two clock signals and a plurality of signals derived from the two clock signals, such as four signals derived from the two clock signals. Desirably, the sample and hold is configured to sample a voltage across a first capacitor while a second capacitor is disconnected from said first capacitor, and is configured to thereafter connect the second capacitor to the first capacitor and discharge at least a portion of a charge held in the first capacitor into the second capacitor. As such, a sample operation is performed when the second capacitor is disconnected from the first capacitor and a hold operation is performed after the second capacitor is connected to the first capacitor.
REFERENCES:
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patent: 4604584 (1986-08-01), Kelley
patent: 5281860 (1994-01-01), Krenik et al.
patent: 5481212 (1996-01-01), Shima
patent: 5506526 (1996-04-01), Seesink
patent: 5698999 (1997-12-01), Etoh et al.
patent: 5714894 (1998-02-01), Redman-White et al.
patent: 5986599 (1999-11-01), Matsuo
patent: 6052000 (2000-04-01), Nagaraj
patent: 6169427 (2001-01-01), Brandt
Cunningham Terry D.
LSI Logic Corporation
Nguyen Long
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