Passive network in the form of a CCRL array

Details Passive network in the form of a CCRL array Passive network in the form of a CCRL array

1999-03-26

2001-06-12

Bettendorf, Justin P. (Department: 2817)

Wave transmission lines and networks

Coupling networks

Frequency domain filters utilizing only lumped parameters

C333S185000

Reexamination Certificate

active

06246300

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a passive network in the form of a chip and, more specifically, to a passive network, such as a CC (Chip-Capacitor) array in the form of a chip, wherein internal conductors of a number of capacitors are lead out at a longitudinal side surface of a chip wafer as terminals and frame electrodes of the capacitors are led out at both frontal side surfaces of the chip wafer.
SUMMARY OF THE INVENTION
According to the present invention, for the creation of CC (Chip Capacitor) arrays, internal conductors of a number of capacitors on one longitudinal side surface of a chip wafer are led out as terminals, while common frame electrodes of the number of capacitors are led out at both side surfaces of the chip wafer.
A CC array constructed according to the present invention can, for example find application for interference suppression at terminal lines of microcontrollers. preferably, in a PLCC (Plastic Leaded Chip Carrier) housing, or in connection with integrated circuits (IC's), hybrid components, and others.
A particular advantage in this construction of a CC array according to the present invention is that terminals which conduct voltage, called “hot” terminals of the individual capacitors, are routed very close to the integrated circuit (IC) and the associated terminals lines can be further routed under the CC array. The routing of the voltage-carrying terminals very close to the integrated circuit satisfies a requirement of experts in the EMI (Electro-Magnetic Interference), field which states that the closer a capacitor is located to the terminals of the integrated circuit, the smaller the required capacitance value can be. For the user, this yields further advantages with respect to a considerable savings of space in relation to individual capacitors, as well as a lower equipping expense.
According to an embodiment of the present invention, corresponding to the provided module design for CCR (Chip-Capacitor-Resistor) arrays, resistance regions additionally need be applied on a surface of a chip wafer only in a number corresponding to the number of capacitors. Terminals of the individual resistance regions are on the one hand, respectively connected with the internal conductor of an allocated capacitor and, on the other hand are led out at the second longitudinal side surface of the chip wafer. Analogous to the above-described embodiment of a CC array according to the present invention, a passive network expanded to form a CCR array also can be used for the suppression of interference on lines. An additional advantage of this embodiment is the higher effectiveness of the RC element or elements created.
In the provided module system, according to the present invention a passive network for CCRL arrays can be created (Chip-Capacitor-Resistor-Inductance) wherein a ferrite wafer is applied on the surface of the above-described resistance layer regions.
By means of this expansion of a passive network in the form of a CCRL array, there results an additional advantage; namely, the higher effectiveness of the CCRL array due to the addition of an inductance L to the RC elements.
In order to achieve a suppression of interference in the RF range, conductors are typically plugged through small ferrite tubes. The effectiveness of open magnetic circuits in which an interconnect is located parallel to the ferrite surface is thus somewhat smaller. For this reason, in the inventive design of a CCRL array the effectiveness of the open magnetic circuits comes into play only in the higher frequency range, i.e., in a frequency range above 100 MHz.
An electrical component in chip form is particularly advantageous when constructed with the depicted passive network, wherein interconnects are arranged on a board, and are connected with a CC array or with a CCR array, and wherein a microcontroller is connected with the interconnects via terminals.
In an arrangement with a CC array, the interconnects are guided through under the CC array. Conversely in an arrangement with a CCR array the interconnects are not led through under the CCR array.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and the Drawing.


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