Passive multiplexing using sparse arrays

Details Passive multiplexing using sparse arrays Passive multiplexing using sparse arrays

1993-09-07

1996-04-16

Fuller, Benjamin R.

Incremental printing of symbolic information

Ink jet

Ejector mechanism

347180, B41J 201

Patent

active

055087248

ABSTRACT:
A multiplexed array of resistors including a plurality of address leads and a plurality of ground leads which cooperatively define a matrix of nodes, each node defining a possible location in the matrix for a resistor heater interconnecting one address lead and one ground lead. Resistor heaters are located in the array at only a portion of the nodes. The locations of the resistor heaters are selected to limit the conductance of alternate current paths around the resistor heater when addressed. The resistor heaters are preferably formed at nodes selected so that no two address leads are interconnected through resistor heaters to more than one common ground lead. Preferably, each alternate current path includes at least four non-addressed resistors in series.

REFERENCES:
patent: 4360818 (1982-11-01), Moriguchi et al.
patent: 4633228 (1986-12-01), Larson
patent: 5144336 (1992-09-01), Yeung

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