Passive element chip and manufacturing method thereof, and...

Details Passive element chip and manufacturing method thereof, and... Passive element chip and manufacturing method thereof, and...

2006-09-05

2006-09-05

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S723000

Reexamination Certificate

active

07102227

ABSTRACT:
A passive element chip permits a reduced size and a higher packaging density to be achieved. The passive element chip has a substrate, a plurality of passive elements formed by metal wires on the substrate, and electrodes for electrically connecting the plurality of passive elements to an external source. The passive elements are isolated from each other.

REFERENCES:
patent: 5111278 (1992-05-01), Eichelberger
patent: 6582991 (2003-06-01), Maeda et al.
patent: 6603210 (2003-08-01), Kishimoto et al.
patent: 6853559 (2005-02-01), Panella et al.
patent: 2002/0122244 (2002-09-01), Sotgiu et al.
patent: 2003/0098505 (2003-05-01), Kimura et al.
patent: 2003/0122244 (2003-07-01), Lin et al.
patent: 2003/0151136 (2003-08-01), Ji
patent: 2004/0021218 (2004-02-01), Hayama et al.
patent: 2002-261449 (2002-09-01), None

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