Registers – Systems controlled by data bearing records – Credit or identification card systems
Reexamination Certificate
1999-03-24
2003-07-22
Frech, Karl D. (Department: 2876)
Registers
Systems controlled by data bearing records
Credit or identification card systems
C235S487000, C235S492000
Reexamination Certificate
active
06595414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a data carrier having receiving means for receiving an amplitude-modulated carrier signal which is amplitude-modulated in dependence on data to be received and which comprises high intervals of high amplitude and pause intervals of reduced amplitude, and having power generating means connected to the receiving means and adapted to generate d.c. power from the received carrier signal, which power generating means include storage means for the storage of generated d.c. power, and having pause detection means connected to the receiving means and adapted to detect pause intervals in the received carrier signal and to generate and supply an identification signal upon detection of a pause interval, and having clock signal generating means connected to the receiving means and adapted to generate a clock signal from the received carrier signal and to supply the generated clock signal, and having data processing means arranged to receive d.c. power from the storage means of the power generating means and the clock signal from the clock signal generating means, which data processing means serve for processing data modulated on the received carrier signal and have only an idle power consumption when no clock signal is applied and an operating power consumption higher than the idle power consumption when a clock signal is applied.
The invention further relates to a circuit comprising the means defined hereinafter, namely power generating means to which a received amplitude-modulated carrier signal can be applied, which carrier signal is amplitude-modulated in dependence on data to be received and which comprises high intervals of high amplitude and pause intervals of reduced amplitude, and which are adapted to generate d.c. power from the received carrier signal and which include storage means for the storage of generated d.c. power, and pause detection means to which the received carrier signal can be applied and adapted to detect pause intervals in the received carrier signal and to generate and supply an identification signal upon detection of a pause interval, and clock signal generating means to which the received carrier signal can be applied and adapted to generate a clock signal from the received carrier signal and to supply the generated clock signal, and data processing means arranged to receive d.c. power from the storage means of the power generating means and the clock signal from the clock signal generating means, which data processing means serve for processing data modulated on the received carrier signal and have only an idle power consumption when no clock signal is applied and an operating power consumption higher than the idle power consumption when a clock signal is applied.
2. Description of the Related Art
Such a data carrier of the type defined in the first paragraph has been in use for a relatively long time in different variants for different applications using a circuit of the type defined in the second paragraph, which circuit is commercially available as an IC from the Applicant, and is consequently known. As regards such a known data carrier and such a known circuit reference can also be made to the document U.S. Pat. No. 5,345,231 A. The disclosure in said document is incorporated herewith by reference to said document.
In the known data carrier the d.c. power necessary for the operation of the data carrier is generated by means of power generating means which essentially comprise a rectifier circuit and a storage capacitor connected to the rectifier circuit. The d.c. power needed in the data carrier is derived from the received carrier signal, of which received carrier signal it is mainly the high portions of high amplitude that contribute to the generation of the d.c. power, while there is hardly any power supply to the storage capacitor of the power generating means in the pause intervals of the carrier signal. However, since in spite of the lacking power supply to the storage capacitor the clock signal generating means generate a clock signal during the pause intervals, the data processing means are clocked and consequently require a comparatively much d.c. power, which is then drained from the storage capacitor while at the same time there is no power supply to the storage capacitor. As a result of this, the d.c. power stored by means of the storage capacitor decreases to an undesirable extent, which in its turn leads to a decrease of the internal supply voltage in the data carrier. This decrease of the supply voltage then ultimately limits the range over which communication is possible between the known data carrier and a write/read station adapted to cooperate with this data carrier.
SUMMARY OF THE INVENTION
It is an object of the invention to preclude the afore-mentioned problem and to provide an improved data carrier and an improved circuit which exhibit hardly any loss in attainable range.
According to the invention, in order to achieve the afore-mentioned object in a data carrier of the type defined in the first paragraph control means have been provided, which include pause detection means and which upon detection of a pause interval cause the application of the clock signal to the data processing means to be inhibited.
According to the invention, in order to achieve the afore-mentioned object in a circuit of the type defined in the second paragraph control means have been provided, which include pause detection means and which upon detection of a pause interval cause the application of the clock signal to the data processing means to be inhibited.
By means of the measures in accordance with the invention it is achieved in a simple and advantageous manner, using the pause detection means which are present anyway, that in those time intervals in which there is no power supply to the storage means of the power storage means, because a pause interval occurs in the carrier signal being received, the supply of the clock signal to the data processing means is inhibited at least for a substantial part, as a result of which there is no unnecessary power consumption in the data processing means, which are energized with d.c. power from the storage means. Thus, it is achieved that the d.c. energy stored in the storage means is reduced only to a comparatively small extent during the pause intervals, as a result of which the internal supply voltage in the data carrier is not reduced significantly and, consequently, there is hardly any adverse effect on the range over which communication is possible between a data carrier in accordance with the invention and a write/read station adapted to cooperate with this data carrier.
With respect to the advantageous variants of a data carrier in accordance with the invention and a circuit in accordance with the invention as defined in the dependent claims it is to be noted that these variants have proved to be advantageous in view of a very simple and reliable implementation.
The afore-mentioned as well as further aspects of the invention will become apparent from the examples of an embodiments described hereinafter and will be elucidated with reference to these examples.
REFERENCES:
patent: 5286955 (1994-02-01), Klosa
patent: 5345231 (1994-09-01), Koo et al.
patent: 5418353 (1995-05-01), Katayama et al.
patent: 5449894 (1995-09-01), Bruhnke et al.
patent: 5898738 (1999-04-01), Nagata et al.
Eber Wolfgang
Thüringer Peter
Frech Karl D.
Koninklijke Philips Electronics , N.V.
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