Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1998-07-14
2003-05-20
Fahmy, Jr., Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S784000
Reexamination Certificate
active
06566737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically to a passivation structure and its method of fabrication.
2. Discussion of Related Art
Integrated circuits are made up of literally millions of individual devices such as transistors and capacitors formed on a semiconductor substrate. The devices are integrated together by alternating conductive and insulating layers to form functional circuits such as microprocessors. The final layer deposited is typically a passivation layer which is an insulating layer which provides protection against mechanical and chemical damage during assembly and packaging.
An example of a conventional passivation structure is shown in FIG.
1
.
FIG. 1
shows a substrate
100
having formed on its outer surface a metal interconnect layer
102
which includes a bond pad
104
and interconnects
106
. A passivation layer
108
which includes a silicon nitride layer
110
and a thick polyimide layer
112
is formed over metal layer
102
as shown in
FIG. 1. A
contact opening
114
is then formed through the silicon nitride layer
110
and the polyimide layer
112
to enable an electrical contact, such as a wire bond
116
, to be made to bond pad
104
to enable the inputting and outputting of external signals to the substrate. Silicon nitride layer
110
, which is a hermetic layer, is formed in direct contact with the lower metal layer
102
to ensure that no moisture path exists to the underlying substrate, especially in the bond pad openings
114
.
Although such a passivation structure provides an excellent hermetic seal of substrate
100
, device performance suffers due to high metal line-to-metal-line capacitance. That is, because silicon nitride layer
110
has a high dielectric constant (approximately 7.0) and because it is formed in gaps
118
between adjacent metal features
104
and
106
, line-to-line capacitive coupling is increased and device performance reduced. Another problem associated with the passivation structure shown in
FIG. 1
is that it is difficult to deposit a silicon nitride layer into high aspect ratio gaps
118
to a thickness necessary to obtain a sufficient hermetic seal.
Thus what is desired is a passivation structure and methodology which forms a hermetic seal and which provides low interconnect capacitance.
SUMMARY OF THE INVENTION
A novel passivation structure and its method of fabrication. According to the present invention a first dielectric layer is formed upon a conductive layer formed over a substrate. The first dielectric layer and the conductive layer are then patterned into a first dielectric capped interconnect and a dielectric capped bond pad. Next, a second dielectric layer is formed over and between the dielectric capped interconnect and the dielectric capped bond pad. The top portion of the second dielectric layer is removed so as to expose the dielectric capped bond pad and the dielectric capped interconnect. A third dielectric layer is then formed over the exposed dielectric capped bond pad and the exposed dielectric capped interconnect and over the second dielectric.
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patent: 5585280 (1996-12-01), Kwasnick et al.
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patent: 5728631 (1998-03-01), Wang
patent: 5923179 (1999-07-01), Taylor
patent: 5985765 (1999-11-01), Hsiao et al.
patent: 5989992 (1999-11-01), Yabu
patent: 63308924 (1988-12-01), None
Blakely , Sokoloff, Taylor & Zafman LLP
Fahmy Jr. Wael
Intel Corporation
Pizarro-Crespo Marcos D.
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