Passivation process and structure for self-alignment with the lo

Details Passivation process and structure for self-alignment with the lo Passivation process and structure for self-alignment with the lo

1980-06-17

1982-06-01

Smith, John D.

Coating processes

Electrical product produced

Welding electrode

204 65, 156653, 156656, 156657, 427 86, 427 88, 427 93, 427 99, 427273, H01L 2124, H01L 21314

Patent

active

043328377

ABSTRACT:
A passivation process and structure with self-alignment with the location of a mask wherein oxygen-doped poly-crystalline silicon is deposited on a semiconductor surface, a part of which is occupied by a silicide or by a silicon-metal eutectic. The sipox deposit is adhesive to the semiconducting parts and not to said part. The invention applies to the miniaturization of semiconductor components and integrated circuits.

REFERENCES:
patent: 3393091 (1968-07-01), Hartmann et al.
patent: 4084986 (1978-04-01), Aoki et al.
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4194934 (1980-03-01), Blaske et al.
Aoki et al., "`SIPOS` A New Technology for Silicon Surface Passivation", JEE, No. 109, p. 44-48, Jan. 1976.
Chapman "Depositing Platinum Silicide Contacts", IBM TDB vol. 15, No. 4, p. 1341, Sep. 1972.
Crowder et al., "Use of Silicides in Overlapping Polysilicon Gate Process" IBM TDB, vol. 20, No. 6, p. 2455, Nov. 1977.

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