Fishing – trapping – and vermin destroying
Patent
1994-03-11
1995-08-01
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437238, 437240, 437919, 437978, H01L 2102
Patent
active
054380235
ABSTRACT:
A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer. Similarly, an optional sealing layer such as silicon dioxide, silicon nitride, or polymer based materials can be deposited on top of the passivation layer to prevent any possible contamination of the integrated circuit package by the passivation layer. Once the hard passivation layer and any optional layers are formed, these layers are etched to provide access to underlying integrated circuit bonding pads.
REFERENCES:
patent: 4040874 (1977-08-01), Yerman
patent: 4149302 (1979-04-01), Cook
patent: 4675715 (1987-06-01), Lepselter et al.
patent: 4757028 (1988-07-01), Kondoh et al.
patent: 4759823 (1988-07-01), Asselamis et al.
patent: 4811078 (1989-03-01), Tigelaar et al.
patent: 4860254 (1989-08-01), Pott et al.
patent: 5024964 (1991-06-01), Rohrer et al.
patent: 5040046 (1991-08-01), Chhabra et al.
patent: 5043049 (1991-08-01), Takenaka
patent: 5081559 (1992-01-01), Fazan et al.
patent: 5119154 (1992-06-01), Gnadinger
patent: 5122923 (1992-06-01), Matsubara et al.
patent: 5124014 (1992-06-01), Foo et al.
patent: 5266355 (1993-11-01), Wernberg et al.
Argos, Jr. George
Spano John D.
Traynor Steven D.
Chaudhuri Olik
Meza Peter J.
Ramtron International Corporation
Tsai H. Jey
LandOfFree
Passivation method and structure for a ferroelectric integrated does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Passivation method and structure for a ferroelectric integrated , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Passivation method and structure for a ferroelectric integrated will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-733714