Passivation layer structure with through-holes for semiconductor

Details Passivation layer structure with through-holes for semiconductor Passivation layer structure with through-holes for semiconductor

1990-07-30

1991-12-03

Hille, Rolf

357 53, 357 54, H01L 2934, H01L 2940

Patent

active

050703862

ABSTRACT:
A passivation layer covering a metal wire and semiconductor surface of a semiconductor integrated circuit composed of a metal-oxide-semiconductor (MOS) type transistor is a double-layer comprising a silicon nitride (P-SiN) layer formed by plasma CVD method and a phosphorus silicide glass (PSG) layer beneath the silicon nitride layer, and the P-SiN layer has a vacant region (a window) at the portion more than 20 .mu.m and less than 100 .mu.m away from an edge of a gate oxide layer of the transistor.

REFERENCES:
patent: 4406053 (1983-09-01), Takasaki et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
"Silicon Processing for the VLSI Era", Wolf, Lattice Press, 1990, pp. 337, 361-362.

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