Passivation for tight metal geometry

Details Passivation for tight metal geometry Passivation for tight metal geometry

1997-12-31

2002-04-02

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S692000, C438S694000, C257S529000

Reexamination Certificate

active

06365521

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of integrated circuit devices and more particularly to the passivation of such devices.
2. Description of Related Art
In general, an integrated circuit chip is made up of millions of individual devices coupled together in an integrated way through conductive metal lines. The interconnection of individual devices requires multiple layers of metal lines, such as for example five metal lines. The individual metal lines are insulated from one another by dielectric material, such as for example silicon dioxide (SiO
2
). Located on the periphery of the integrated circuit chip are bond pads. To activate the circuitry within the chip, it is necessary to supply a voltage to the bond pads. These voltage signals are supplied to the bond pads through a package to which the integrated circuit device is affixed. After the chip is affixed to a package, individual bond wires are used to electrically couple each bond pad to a corresponding pad on a package substrate. Each corresponding pad on a package substrate is then individually coupled to an external pin. The packaged integrated circuit device may then be placed within a socket in order to electrically couple the external pins to drivers that supply the necessary voltage signal to activate the integrated circuit chip.
In general, overlying the periphery of the chip is a passivation layer through which bond pad openings are formed. The main purpose of the passivation layer is to provide electrical stability to a chip by isolating the chip surface from electrical and chemical conditions in the environment. The passivation layer must also protect the device from mechanical damage during all assembly and packaging operations.
Today, the most common method used to produce a passivation layer on the periphery of a chip is by chemical vapor deposition of silicon nitride (Si
3
N
4
) and/or silicon oxynitride (SiO
x
N
y
) with silicon nitride providing better isolation from the exterior environment than silicon oxynitride. Silicon nitride and silicon oxynitride are preferred choices because these materials protect the integrated circuit device better from environmental to effects, particularly moisture, than other dielectric materials, such as SiO
2
. Chemical vapor deposited silicon nitride, for example, exhibits little or no permeability to moisture as noted, for example, in “Silicon Processing for the VLSI Era,” Volume 1-Process Technology, Wolf, S. and Tauber, R. N., Lattice Press, 1986, pages 191-94.
In order to provide a necessary level of isolation and protection, particularly from moisture, a certain thickness of silicon nitride and/or silicon oxynitride passivation layer must be deposited. The thickness of the layer depends on the needed sidewall and bottom coverage of the ultimate layer of metal lines. One conventional standard is a passivation layer of at least 0.2 microns (&mgr;m). Current chemical vapor deposition (CVD) methods allow the achievement of this degree of step coverage for a minimum space between final metal lines of approximately 1 &mgr;m or more. As geometries decrease, the space between metal lines also decreases which causes inadequate step coverage by the passivation layer over the final metal lines.
FIG. 1
shows a schematic, planar side view of a portion of an integrated circuit structure having three metal lines,
1
,
2
and
3
atop substrate
10
. Overlying metal lines
1
,
2
, and
3
is a conformally-deposited passivation layer
15
of silicon nitride or silicon oxynitride. In
FIG. 1
, the distance between metal line
1
and metal line
2
is less than 1.0 &mgr;m while the distance between metal lines
2
and
3
is greater than 1.0 &mgr;m.
FIG. 1
shows that the step coverage between metal lines
1
and
2
as a result of the non-conformal deposition of silicon nitride or silicon oxynitride, is less than desired, for example less than 0.2 &mgr;m. This follows because during the CVD deposition, the silicon nitride or silicon oxynitride is “pinched-off” between metal lines
1
and
2
and therefore cannot achieve the desired step coverage. This pinching-off causes a tunnel
20
to be formed between metal lines
1
and
2
.
The deposition between metal lines
1
and
2
is to be compared with the deposition between metal lines
2
and
3
. Between metal lines
2
and
3
, the CVD deposition of silicon nitride or silicon oxynitride
15
does not get pinched-off due to the spacing geometry between metal lines
2
and
3
which is greater the 1.0 &mgr;m. Thus, a portion of metal line
2
and metal line
3
receive adequate step coverage of passivation layer
15
.
FIG. 2
shows a schematic, perspective top view of integrated circuit structure
10
and metal lines
1
and
2
. In
FIG. 2
, metal lines
1
and
2
are patterned to turn approximately 90° atop integrated circuit structure
10
. This turn would be associated with, for example, coupling to bond pads
25
and
30
, respectively. In
FIG. 2
, metal lines
1
and
2
are patterned to be less than 1.0 &mgr;m apart.
FIG. 2
shows pinching-off of the CVD deposition of silicon nitride or silicon oxynitride
15
between metal lines
1
and
2
. This pinching-off creates a tunnel
20
between the metal lines
1
and
2
. If this tunnel is open as, for example, when the metal lines are coupled to bond pads
25
and
30
, respectively, environmental impurities, such as for example moisture, can get in tunnel
20
and attack metal lines
1
and
2
at areas having insufficient step coverage.
One prior art method to improve the step coverage over the top metal lines involves the deposition of an oxide prior to as the deposition of the silicon nitride or silicon oxynitride.
FIG. 3
is an example of such a prior art method.
FIG. 3
shows a schematic, planar side view of an integrated circuit structure
35
having metal lines
36
and
37
on the top surface or periphery of integrated circuit structure
35
together with bond pad
38
. In
FIG. 3
, metal lines
36
and
37
and bond pad
38
are insulated by an oxide
40
, such as for example CVD-deposited SiO
2
. Overlying SiO
2
layer
40
is silicon nitride or silicon oxynitride layer
45
. In
FIG. 3
, an opening
50
has been etched to bond pad
38
to allow connection to bond pad
38
by an integrated circuit package (not shown).
As illustrated in
FIG. 3
, a CVD-deposited SiO
2
provides excellent step coverage over metal lines
36
and
37
. Unfortunately, oxide does not provide the necessary moisture barrier properties demonstrated by silicon nitride or silicon oxynitride. Accordingly, as shown in
FIG. 3
, once opening
50
is made to bond pad
38
, moisture can attack oxide
40
and travel to metal lines
36
and
37
and have deleterious effects on metal lines
36
and
37
. Thus, although metal lines
36
and
37
possess adequate step coverage properties, the step coverage is of a material that will not protect the metal lines from attack by environmental effects such as moisture.
SUMMARY OF THE INVENTION
A method of passivating an integrated circuit is disclosed. The method includes providing an integrated circuit having a top side including a bond pad, depositing a first dielectric over the top side of the integrated circuit, exposing a first area portion of a top side of the bond pad, depositing a second dielectric of a material that is substantially impermeable to moisture over the top side of the integrated circuit, and exposing a second area portion of the top side of the bond pad, the second area portion within the first area portion.
Other features and advantages of the invention are described herein with reference to the figures and the detailed description.


REFERENCES:
patent: 5294295 (1994-03-01), Gabriel
patent: 5302551 (1994-04-01), Iranmanesh et al.
patent: 5445996 (1995-08-01), Kodera et al.
patent: 5502007 (1996-03-01), Murase
patent: 5629242 (1997-05-01), Nagashima et al.
patent: 5639697 (1997-06-01), Weling et al.
patent: 5798298 (1998-08-01), Yang et al.
patent: 5844295 (1999-11-01)

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