Passivation etching procedure, using a polysilicon stop layer, f

Details Passivation etching procedure, using a polysilicon stop layer, f Passivation etching procedure, using a polysilicon stop layer, f

1998-11-16

2000-01-25

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438723, 438735, 438740, 438751, 438756, 438787, H01L 21465

Patent

active

060178248

ABSTRACT:
A process of opening, a stack of large diameter via holes, in a multiple levels of insulator layers, to be used for access of a laser repair procedure, applied to underlying integrated circuit shapes, while simultaneously opening small diameter via holes, in the same multiple levels of insulator layers, to be used to accommodate metal plug structures, has been developed. The process features the use of a polysilicon stop layer, used at the bottom of the stack of large diameter via holes, protecting underlying components of the underlying integrated circuit, from the dry and wet etching procedures used for the creation of the stack of large diameter via holes. The process also features the formation of metal spacers, on the sides of the large diameter via holes, created simultaneously during the formation of metal plug structures, and used again to protect the multiple levels of insulator layer, that would have been exposed, if left unprotected, during a wet etching procedure.

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patent: 5641701 (1997-06-01), Fukuhara et al.
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