Passivated V-gate GaAs field-effect transistor and fabrication p

Details Passivated V-gate GaAs field-effect transistor and fabrication p Passivated V-gate GaAs field-effect transistor and fabrication p

1978-03-06

1980-03-18

Tupman, W. C.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 357 91, B01J 1700

Patent

active

041931823

ABSTRACT:
The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implanatation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region. Schottky-gate metallization is then deposited in this V-shaped groove to form the Schottky-gate electrode of the device, and the fully passivated device thus formed exhibits excellent source and drain contact resistance and a minimum of drain-to-gate capacitance.

REFERENCES:
patent: 3413531 (1968-11-01), Leith
patent: 3523042 (1970-08-01), Bower
patent: 3775191 (1973-11-01), McQuhae
patent: 4003126 (1977-01-01), Holmes

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