Passivated V-gate GaAs field-effect transistor

Details Passivated V-gate GaAs field-effect transistor Passivated V-gate GaAs field-effect transistor

1977-02-07

1979-05-29

Wojciechowicz, Edward J.

357 23, 357 55, 357 68, H01L 2980

Patent

active

041568796

ABSTRACT:
The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implantation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region. Schottky-gate metallization is then deposited in this V-shaped groove to form the Schottky-gate electrode of the device, and the fully passivated device thus formed exhibits excellent source and drain contact resistance and a minimum of drain-to-gate capacitance.

REFERENCES:
patent: 3975752 (1976-08-01), Nicolay
patent: 3986196 (1976-10-01), Decker et al.
patent: 4029522 (1977-06-01), De La Moneda
patent: 4049476 (1977-09-01), Horie
patent: 4053915 (1977-10-01), Cave

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