Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2003-08-22
2008-09-23
Pizarro, Marcos D. (Department: 2814)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C257SE43006, C365S158000
Reexamination Certificate
active
07427514
ABSTRACT:
A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.
REFERENCES:
patent: 3623032 (1971-11-01), Schapira
patent: 3623035 (1971-11-01), Kobayashi et al.
patent: 3816909 (1974-06-01), Maeda et al.
patent: 3947831 (1976-03-01), Kobayashi et al.
patent: 4044330 (1977-08-01), Johnson et al.
patent: 4060794 (1977-11-01), Feldman et al.
patent: 4158891 (1979-06-01), Fisher
patent: 4455626 (1984-06-01), Lutes
patent: 4731757 (1988-03-01), Daughton et al.
patent: 4780848 (1988-10-01), Daughton et al.
patent: 4801883 (1989-01-01), Muller et al.
patent: 4849695 (1989-07-01), Muller et al.
patent: 4945397 (1990-07-01), Schuetz
patent: 5039655 (1991-08-01), Pisharody
patent: 5064499 (1991-11-01), Fryer
patent: 5140549 (1992-08-01), Fryer
patent: 5496759 (1996-03-01), Yue et al.
patent: 5547599 (1996-08-01), Wolfrey et al.
patent: 5569617 (1996-10-01), Yeh et al.
patent: 5587943 (1996-12-01), Torok et al.
patent: 5650958 (1997-07-01), Gallagher et al.
patent: 5691228 (1997-11-01), Ping et al.
patent: 5701222 (1997-12-01), Gill et al.
patent: 5721171 (1998-02-01), Ping et al.
patent: 5726498 (1998-03-01), Licata et al.
patent: 5741435 (1998-04-01), Beetz, Jr. et al.
patent: 5744398 (1998-04-01), Byun et al.
patent: 5756366 (1998-05-01), Berg et al.
patent: 5756394 (1998-05-01), Manning
patent: 5792687 (1998-08-01), Jeng et al.
patent: 5795823 (1998-08-01), Avanzino et al.
patent: 5851875 (1998-12-01), Ping et al.
patent: 5861328 (1999-01-01), Tehrani et al.
patent: 5869389 (1999-02-01), Ping et al.
patent: 5882979 (1999-03-01), Ping et al.
patent: 5899742 (1999-05-01), Sun
patent: 5926394 (1999-07-01), Nguyen et al.
patent: 5939758 (1999-08-01), Arima
patent: 5945350 (1999-08-01), Violette et al.
patent: 5956267 (1999-09-01), Hurst et al.
patent: 5982658 (1999-11-01), Berg et al.
patent: 5994193 (1999-11-01), Gardner et al.
patent: 6028786 (2000-02-01), Nishimura
patent: 6048739 (2000-04-01), Hurst et al.
patent: 6100185 (2000-08-01), Hu
patent: 6110812 (2000-08-01), Ho et al.
patent: 6130145 (2000-10-01), Ilg et al.
patent: 6136705 (2000-10-01), Blair
patent: 6153443 (2000-11-01), Durlam et al.
patent: 6156630 (2000-12-01), Iyer
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6174764 (2001-01-01), Manning
patent: 6211054 (2001-04-01), Li et al.
patent: 6211090 (2001-04-01), Durlam et al.
patent: 6218302 (2001-04-01), Braeckelmann et al.
patent: 6255701 (2001-07-01), Shimada
patent: 6291891 (2001-09-01), Higashi et al.
patent: 6338899 (2002-01-01), Fukuzawa et al.
patent: 6358756 (2002-03-01), Sandhu et al.
patent: 6379978 (2002-04-01), Goebel et al.
patent: 6391658 (2002-05-01), Gates et al.
patent: 6392922 (2002-05-01), Liu
patent: 6440753 (2002-08-01), Ning et al.
patent: 6485989 (2002-11-01), Signorini
patent: 6500710 (2002-12-01), Nakagawa
patent: 6623987 (2003-09-01), Liu
patent: 6630718 (2003-10-01), Trivedi
patent: 6806546 (2004-10-01), Liu
patent: 2002/0041514 (2002-04-01), Scheler et al.
patent: 2002/0048946 (2002-04-01), Tang et al.
patent: 198 36 567 A 1 (2000-02-01), None
patent: 0 776 011 (1997-05-01), None
patent: 2000-30222 (2000-01-01), None
patent: WO98/20496 (1998-05-01), None
patent: WO 00/19440 (2000-04-01), None
Pohm et al., “Experimental and Analytical Properties of 0.2 Micron Wide, Multi-Layer, GMR, Memory Elements,”IEEE Transactions on Magnetics, vol. 32, No. 5, Sep. 1996, pp. 4645-4647.
Prinz, Gary, “Magnetoelectronics,”Science, vol. 282, Nov. 27, 1998, pp. 1660-1663.
Wang, Zhi G. et al., “Feasibility of Ultra-Dense Spin-Tunneling Random Access Memory,”IEEE Transactions on Magnetics, vol. 33, No. 6, Nov. 1997, pp. 4498-4512.
Razavi et al., “Design Techniques for High-Speed, High-Resolution Comparators”,IEEE Journal of Solid State Circuit, vol. 27, No. 12, Dec. 1992.
Kaakani, H., “Non-Volatile Memory (MRAM) ANXXX,” [online], Honeywell, Mar. 1999 [retrieved on Aug. 2, 2007]. Retrieved from the Internet: <URL: www.ssec.honeywell.com/avionics/h—gmr.pdf>.
USPTO, Office Action from U.S. Appl. No. 09/638,419, paper mailed Jun. 4, 2001.
APPLICANT, Response to Office Action from U.S. Appl. No. 09/638,419, paper dated Oct. 3, 2001.
USPTO, Office Action from U.S. Appl. No. 09/638,419, paper mailed Dec. 28, 2001.
APPLICANT Response to Office Action from U.S. Appl. No. 09/638,419, paper dated Jan. 25, 2002.
USPTO, Office Action from U.S. Appl. No. 10/057,162, paper mailed Feb. 26, 2003.
APPLICANT, Response to Office Action from U.S. Appl. No. 10/057,162, paper dated Apr. 1, 2003.
USPTO, Office Action from U.S. Appl. No. 10/078,234, paper mailed Nov. 15, 2002..
APPLICANT, Response to Office Action from U.S. Appl. No. 10/078,234, paper dated Feb. 17, 2003.
USPTO, Office Action from U.S. Appl. No. 10/078,234, paper mailed Mar. 10, 2003.
APPLICANT, Response to Office Action from U.S. Appl. No. 10/078,234, paper dated Apr. 9, 2003.
USPTO, Advisory Action from U.S. Appl. No. 10/078,234, paper mailed Apr. 22, 2003.
APPLICANT, Amendment under 37 C.F.R. § 1.114 (RCE) from U.S. Appl. No. 10/078,234, paper dated Jun. 26, 2003.
USPTO, Office Action from U.S. Appl. No. 10/078,234, paper mailed Jul. 28, 2003.
APPLICANT, Response to Office Action from U.S. Appl. No. 10/078,234, paper dated Oct. 28, 2003.
USPTO, Office Action from U.S. Appl. No. 10/078,234, paper mailed Dec. 16, 2003.
APPLICANT, Response to Office Action from U.S. Appl. No. 10/078,234, paper dated Jan. 22, 2004.
USPTO, Office Action from U.S. Appl. No. 10/873,363, paper mailed May 3, 2005.
APPLICANT, Response to Office Action from U.S. Appl. No. 10/873,363, paper dated Aug. 3, 2005.
USPTO, Office Action from U.S. Appl. No. 10/873,363, paper mailed Oct. 5, 2005.
APPLICANT, Appeal Brief from U.S. Appl. No. 10/873,363, paper dated Mar. 3, 2006.
USPTO, Examiner's Answer to Appeal Brief from U.S. Appl. No. 10/873,363, pape mailed Apr. 6, 2006.
APPLICANT, Reply Brief from U.S. Appl. No. 10/873,363, paper dated Jun. 6, 2006.
USPTO; Decision on Appeal for U.S. Appl. No. 10/873,363, Filed Jun. 21, 2004; Decision dated Sep. 26, 2007.
Berg Lonny
Drewes Joel
Larson William L.
Li Shaoping
Liu Harry
LandOfFree
Passivated magneto-resistive bit structure and passivation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Passivated magneto-resistive bit structure and passivation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Passivated magneto-resistive bit structure and passivation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3986099