Passivated copper line semiconductor device structure

Details Passivated copper line semiconductor device structure Passivated copper line semiconductor device structure

2000-09-27

2001-07-03

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S662000, C257S751000, C257S758000, C257S774000, C257S915000

Reexamination Certificate

active

06255734

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to copper electrical conductors on a thin film semiconductor device and more particularly to an passivation of an exposed surface of a copper conductor.
2. Description of Related Art
U.S. Pat. No. 5,420,069 of Joshi et al. for “Method of Making Corrosion Resistant, Low Resistivity Copper for Interconnect Metal Lines” shows a copper line with Cu
3
Ge layers on the sidewalls and top. It shows a “corrosion resistant thin film interconnect material, comprising a bilayer formed of a copper (Cu) film over which a layer of Cu
3
Ge or copper germanium,(Ge) alloy has been deposited.” In
FIG. 3B
, Joshi et al. “. . . shows Cu—Ge passivation layer
180
on all exposed surfaces of copper.” This provides “excellent passivation properties”. The preferred process described is “selective deposition of germanium over copper surfaces . . . exposing the original Copper (Cu) layer (or surface) at a low pressure (0.5 Torr to 1 Torr) to a source of germanium, e.g. GeH
4
gas, in a chemical vapor deposition (CVD) reactor at temperatures ranging from about 200°-450° C. to convert the outer surface of the Cu lines to Cu(x)Ge(y) or Cu
3
Ge . . . . Any Ge containing gas source, e.g. GeH
4
, GeH
6
and the like can be used . . . . It is noted that by increasing the partial pressure of GeH
4
more than 0.1 Torr, the Cu(x)Ge(y) alloy can be changed to Cu
3
Ge or additional Ge can be formed.” Copper “rich phases and . . . specifically Cu
3
Ge may also be produced by plating (electrolytic and electroless), sintered powder and sputtered bilayers which are subsequently reacted.
U.S. Pat. No. 5,288,456 of Aboelfotoh et al. for “Compound with Room Temperature Electrical Resistivity Comparable to that of Elemental Copper” shows a process for producing copper germanide Cu
3
Ge compound on the surface of a silicon substrate which had been treated by evacuation to a pressure of 1×10
−7
Torr for a period of time following which Ge, Ga and copper were deposited sequentially in an evacuated chamber at room temperature to avoid contact with air or oxygen. A thin film of 700 Å of germanium (Ge) was deposited on a <100> surface of the silicon substrate. Then 5-10 atomic percent of gallium (Ga) was deposited on the Ge film followed by deposition of copper (Cu) to a thickness of about 1300 Å. Then the result of the process to this point is annealed at a temperature of about 400° C. in situ for 30 minutes in vacuum. The result is a thin layer of the Ge
3
Cu compound with a thickness of about 2000 Å thickness on the surface which has 1-2% of Ga incorporated therein.
U.S. Pat. No. 5,731,245 of Joshi et al. for “High Aspect Ratio Low Resistivity Lines/Vias with Tungsten Alloy Hard Cap” discusses copper/germanium barrier layers.
U.S. Pat. No. 5,060,050 of Tsuneoka et al. for “Semiconductor Integrated Circuit Device” shows a copper wire process.
Copper, due to the lack of its self-passivation as the result of oxidation, is easily oxidized throughout a copper film which is unsatisfactory for copper conductor lines.
In the past, various techniques for surface-passivation of copper have been proposed.
We find that direct selective CVD growth on the top surface and sidewalls of a copper (Cu) line to form a Cu
3
Ge layer thereon will lead to the problem of poor coverage at the top corner.
SUMMARY OF THE INVENTION
This invention teaches the selective growth of a copper germanide (Cu
3
Ge) compound layer on the sidewalls of a copper (Cu) line, but not on material covering the top of the line which is protected by a cap which does not react with germanium. In addition, preferably, the adhesion layer, upon which the copper line is formed, does not react with germanium when exposed thereto.
In accordance with one aspect of this invention, A method of forming a copper conductor for a thin film electronic device comprises first forming layers over a conductor into a stack, as follows:
a) forming a barrier layer superjacent to the substrate,
b) then forming a copper layer superjacent to the barrier layer,
c) then forming a hard mask layer superjacent to the copper layer,
d) then forming a mask superjacent to the hard mask layer to pattern the stack and etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed.
Then, a copper germanide (Cu
3
Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line. The device is exposed to in situ to germane GeH
4
gas at a temperature from about 200° C. to about 400° C., in an atmosphere of hydrogen/helium (H
2
/He) gases to form the copper germanide (Cu
3
Ge) compound. The barrier layer comprises a material selected from the group consisting of Ta, Ta/TaN, TaN, Ta/TaN/Ta, TaN/Ta, WN
x
, W, and TiN. The hard mask layer comprises a material selected from the group consisting of Ta, Ta/TaN, TaN, Ta/TaN/Ta, TaN/Ta, WN
x
, W, and TiN.
In accordance with another aspect of this invention, a copper conductor line formed into a stack over a substrate comprises a barrier layer superjacent to the substrate, a copper layer superjacent to the barrier layer, a hard mask layer superjacent to the copper layer, the hard mask layer, the copper layer and the barrier layer patterned into a copper conductor line with sidewalls on the copper conductor line, and a copper germanide (Cu
3
Ge) passivation layer selectively grown only on the sidewalls of the copper conductor line.
Preferably, the barrier layer comprises a material selected from the group consisting of Ta, Ta/TaN, TaN, Ta/TaN/Ta, TaN/Ta, WN
x
, W, and TiN, and the hard mask layer comprises a material selected from the group consisting of Ta, Ta/TaN, TaN, Ta/TaN/Ta, TaN/Ta, WN
x
, W, and TiN.


REFERENCES:
patent: 6046108 (2000-04-01), Liu et al.
patent: 6130162 (2000-10-01), Liu et al.
patent: 6143657 (2000-11-01), Liu et al.
patent: 6181013 (2001-01-01), Liu et al.

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