Pass transistors with minimized capacitive loading

Details Pass transistors with minimized capacitive loading Pass transistors with minimized capacitive loading

2007-09-25

2007-09-25

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S091000

Reexamination Certificate

active

10980021

ABSTRACT:
A tracking switch includes an MOS switching transistor with a control terminal coupled to a CMOS inverter. The relative geometries of the transistors that make up the inverter are significantly imbalanced, resulting is substantially different drive strengths (i.e., substantially different on-resistances). The gate of the switching transistor exhibits parasitic capacitances between its current-handling terminals and its control terminal. When the switching transistor is on, these capacitances shunt a portion of the switched signal to a power-supply node, with the problem increasing with the frequency of the propagated signal. The geometry of the transistor used to turn on the switching transistor is selected to produce a high on-resistance, which introduces a high-impedance path from the control terminal of the switching transistor to ground when the switch is closed. The high-impedance path isolates the control terminal of the switching transistor from the supply, thus mitigating the capacitive loading effects of the parasitic capacitors. The transistor used to turn off the switching transistor has a much lower on-resistance than the transistor used to bias the switching transistor on, preventing undesirable signal feed-through from occurring when the switching transistor is off.

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