Partitioning prefetch registers to prevent at least in part...

Details Partitioning prefetch registers to prevent at least in part... Partitioning prefetch registers to prevent at least in part...

2006-11-28

2006-11-28

Fleming, Fritz (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

C712S228000, C712S229000

Reexamination Certificate

active

07143267

ABSTRACT:
A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.

REFERENCES:
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6073215 (2000-06-01), Snyder
patent: 6832296 (2004-12-01), Hooker
patent: 2003/0033509 (2003-02-01), Leibholz et al.

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