Partitioning of virtual addressing memory

Details Partitioning of virtual addressing memory Partitioning of virtual addressing memory

1994-04-18

1995-11-28

Robertson, David L.

Boots, shoes, and leggings

395450, 395415, 39549704, 3642306, 364DIG1, G06F 1210, G06F 1200

Patent

active

054715997

ABSTRACT:
A computer memory system having partitioned page address for instructions and operands. The partitioning scheme for the virtual addressing memory minimizes the delay between the translation logic and the page translation RAMs. Computer processor performance is delayed by only a single clock cycle by the sharing of the memory address bus control between two address processors.

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Memory Chip Organizations for Improved Reliability in Virtual Memories by S. K. Kwon, et al., IBM T D B, vol. 25, No. 6, Nov. 1982, pp. 2952-2957.
"Translation--Lookaside Buffer Consistency" by Patricia J. Teller, IEEE Computer (1990) pp. 26-36.

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