Partitioning of Boolean logic equations into physical logic devi

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364402, 36446401, G06F 1560

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051405261

ABSTRACT:
An automated system for partitioning a set of Boolean logic equations onto one or more devices selected from a plurality of commercially available devices. The system utilizes a processor having a memory containing information on the different architectural types of devices, physical device information on individual devices and user generated design constraints, weighting factors and partitioning directives. Based upon this stored information, the system of the present invention selects all acceptable architectural types of devices wherein at least one of the Boolean logic equations can be placed thereon. For all physical devices associated with the acceptable architectural types only those devices which fall within the selected user constraints are selected. The system then evaluates the weighting factors to order the devices in order of cost value and then fits the equations according to the partitioning directives to the devices. During the fitting process, an optimum device solution is attained having a least cost value for which the system produces an output map suitable for the user of the system to configure the selected devices to implement the set of equations.

REFERENCES:
patent: 3617714 (1971-11-01), Kernighan
patent: 4638442 (1987-01-01), Bryant et al.
patent: 4701860 (1987-10-01), Mader
patent: 4831543 (1989-05-01), Mastellone
patent: 4835709 (1989-05-01), Tsai
patent: 4896272 (1990-01-01), Kurosawa
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 4964056 (1990-10-01), Bekki et al.
patent: 5031111 (1991-07-01), Chao et al.
patent: 5038294 (1991-08-01), Arakawa et al.
patent: 5050091 (1991-09-01), Rubin
Waterman, A Guide to Expert Systems, Addison-Wesley Pub. Co., 1986, pp. 253-259.
Electronic Design, Jun. 11, 1987, Kim, "Artificial Intelligence Helps Cut ASIC Design Time" pp. 107-110.
Bergamaschi, "Automatic Synthesis and Technology Mapping of Combinational Logic", IEEE Int. Conf. on Computer-Aided Design: ICCAD-89, Santa Clara, CA, Nov. 7-10, 1988, pp. 466-469.
EDN, vol. 30, No. 11, Everett, "CAE Tools for Analog Design Are Emerging, But Breadboarding Remains Essential", p. 61 (abstract only), May 16, 1985.
Conference: Data Processing in Design '86, Munich, W. Germany, Oct. 28, 1986, Emberger, "CAD from Circuit Diagram to Factory Documents for the Manufacture of Printed Circuit Boards", pp. 71-86, vol. 4.
Dror et al., "Design of Electrical and Electronic Circuits Using Interactive Computer Graphics", Conference: 1977 Electrical and Electronic Engineers in Israel Tenth Convention, Tel-Aviv, Israel (Oct. 10-13, 1977).
Garrison et al., "Automatic Area Performance Optimization of Combinatorial Logic", IEEE International Conference on Computer-Aided Design, ICCAD-84, Santa Clara, CA, Nov. 12-15, 1984 (abstract).
Theeuwen et al., "Automatic Generation of Boolean Expressions in NMOS Technology", IEEE International Conference on Computer-Aided Design: ICCAD-85, Santa Clara, CA, Nov. 18-21, 1985 (abstract).
Morgan, "Model--An HDL for IC Design", Proceedings of the Third Silicon Design Conference, London, England, Jul. 15-17, 1986 (abstract).
Detjens et al., "Technology Mapping in MIS", IEEE International Conference on Computer Aided Design: ICCAD-87, Santa Clara, CA, Nov. 9-12, 1987 (abstraact).

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