Partitioning of binary quad word format multiply instruction on

Details Partitioning of binary quad word format multiply instruction on Partitioning of binary quad word format multiply instruction on

1998-03-05

2000-02-01

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708510, G06F 744, G06F 738

Patent

active

060214228

ABSTRACT:
There is a unique partitioning problem in determining how to execute the floating point multiply instruction defined by IEEE 754 standard for the quad word format on a S/390 processor. Several manufacturers including IBM and HP define the binary quad word format to have a 113 bit significand. IBM S/390 hexadecimal long floating point format has a 56 bit significand and most S/390 floating point units only contain a long format multiplier. Quad word format multiplication must be executed as a series of several long precision multiplications and extended precision or long precision additions. The S/390 hexadecimal quad word format is easier to implement than binary format since it has a 112 bit significand and can easily be partitioned into two 56 bit parts. But a 113 bit significand would just exceed two partitions and require a third. For extended precision multiplies each partition is multiplied by each other, so if there are two partitions only four multiplies are required but for three partitions this increases to nine multiplies. Methods for partitioning are disclosed here.

REFERENCES:
patent: 4594679 (1986-06-01), George et al.
patent: 5687106 (1997-11-01), Schwarz et al.
patent: 5740093 (1998-04-01), Sharangpani
patent: 5909385 (1999-06-01), Nishiyama et al.
"CMOS Floating-Point Unit For The S/390 Parallel Enterprise Server G4" by Schwarz et al., IBM Journal of Research and Development, vol. 41, No. 4/5, Jul./Sep. 1997, pp. 475-488.
"Hardware Implementation of Sine/Cosine Polynomial Approximation" by Desrosiers et al., IBM TDB, vol. 37, No. 11, Nov. 1994, pp. 609-613.

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