Partitioned parity check and regeneration circuit

Details Partitioned parity check and regeneration circuit Partitioned parity check and regeneration circuit

1989-09-06

1991-09-10

Beausoliel, Robert W.

Excavating

G06F 1110

Patent

active

050480243

ABSTRACT:
A novel partitioned parity check and regeneration circuit is provided for receiving an input data word which is partitioned and the partitioned bits are stored in a partitioning register to provide a subset input data word of fewer data bits than the input data word. Parity register means including a parity register are associated with the partitioning register to provide a parity check of the partitioned data word and for generating an error detect signal when the data bits in the partitioning register are not properly latched. The parity bits stored in the associated parity register are employed with associated output logic to generate regenerated parity bits associated with the output of the data bits in the partitioning register to preserve the integrity of the data.

REFERENCES:
patent: 4371929 (1983-02-01), Brann
patent: 4443876 (1984-04-01), Ng
patent: 4456976 (1984-06-01), Savage
patent: 4462102 (1984-07-01), Povlick
patent: 4556978 (1985-12-01), Kregness
patent: 4697233 (1987-09-01), Scheuneman
patent: 4706250 (1987-11-01), Patel

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