Partitioned adder tree supported by a multiplexer configuration

Details Partitioned adder tree supported by a multiplexer configuration Partitioned adder tree supported by a multiplexer configuration

1998-06-19

2001-09-04

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S625000

Reexamination Certificate

active

06286023

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microprocessor technology, and more specifically, the present invention relates the use of an arithmetic logic unit (ALU) to perform a variety to multiplication formats.
BACKGROUND OF THE INVENTION
The multiplication of two values is a common operation performed in arithmetic logic units. A conventional multiplier (e.g., a 16×6 multiplier) receives a 16-bit multiplicand and a 16-bit multiplier and generates a 32-bit product using a Wallace tree.
The multiplier requires input values of a fixed bit length of 16 bits each. In order to multiply values having other bit length (e.g., a 4×4 multiplication), the input values must be bit extended with additional bits having no additional information. For example, if a 4×4 operation is to be performed, the 4-bit input values must be extended to 16 bits before multiplication. The additional 12 bits of each input have no useful information resulting in the 32-bit product having 24 bits of useless information.
Furthermore, the current multiplier is limited in that it only performs multiplication in series, one multiplication per operation cycle.
Therefore, what is desired is a circuit and method which 1) increase the input bit size format flexibility of the multiplier thereby reducing input value bit extension, and 2) allow for several multiplications to be performed in parallel using a single multiplier.
SUMMARY OF THE INVENTION
A circuit has a partitioned adder tree having first and second parts. A multiplexer is configured such that a bit group represented at the output terminal of the multiplexer is represented at the first part of the partitioned adder tree. A second multiplexer is configured such that a bit group represented at its output terminal is also represented at the second part of the partitioned adder tree.
The two multiplexers provide the same bits groups at their respective output terminals in response to a first instruction. The two multiplexers provide a different bit group at their respective output terminals in response to a second instruction.
The circuit may also include a third and fourth multiplexer. The third multiplexer is configured such that the bit group represented at its output terminal is represented at the first part of the partitioned adder tree. The fourth multiplexer is configured such that the bit group represented at its output terminal is represented at the second part of the partitioned adder tree. The third and fourth multiplexers provide bit groups representing portions of the same value in response to the first instruction. The third and fourth multiplexers provide bit groups representing different values in response to the second instruction.
A method includes providing an identical bit group to each of a first and second part of a partitioned adder tree in response to a first instruction; and providing different bit groups to the first and second parts of the partitioned adder tree in response to a second instruction.
The above circuit and method provide for a partitioned adder tree that multiplies using a variety of input bit size formats. Furthermore, several multiplications may be performed in parallel in the same partitioned adder tree.


REFERENCES:
patent: 4754421 (1988-06-01), Bosshart
patent: 5742538 (1998-04-01), Guttag et al.
patent: 5764558 (1998-06-01), Pearson et al.

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