Partially underfilled solder grid arrays

Details Partially underfilled solder grid arrays Partially underfilled solder grid arrays

2008-04-15

2010-11-23

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S781000, C257S780000, C257S778000, C257SE23021

Reexamination Certificate

active

07839002

ABSTRACT:
An electronic device. The device including a module having opposite top surface and bottom surfaces; a first set of pads on the top surface of the module and a second set of pads on the bottom surface of the module substrate, wires within the module electrically connecting the first set of pads to the second set of pads; a set of solder interconnects in electrical and physical contact with a the second set of module pads; and a dielectric underfill layer formed on the bottom surface of the module, the underfill layer filling the space between lower regions of the solder interconnects of the set of solder interconnects, upper regions of the solder interconnects of the set of solder interconnects extending past a top surface of the underfill layer.

REFERENCES:
patent: 6779783 (2004-08-01), Kung et al.
patent: 6906425 (2005-06-01), Stewart et al.
patent: 2002/0050407 (2002-05-01), Sohn et al.
patent: 2005/0023704 (2005-02-01), Lin et al.
patent: 2009/0057901 (2009-03-01), Lin et al.
patent: 2010/0007019 (2010-01-01), Pendse

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