Partially relaxable composite dielectric structure

Details Partially relaxable composite dielectric structure Partially relaxable composite dielectric structure

1985-12-11

1987-08-18

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 12, 357 2315, 357 54, 365182, 365185, H01L 2978

Patent

active

046880780

ABSTRACT:
Unique EPROM and EEPROM devices are provided with a composite dielectric layer between the control gate and the floating gate which is sufficiently thick to provide electrical and physical integrity but also has a high equivalent dielectric constant. The use of the composite dielectric layer alleviates certain problems experienced in the prior art EPROM and EEPROM devices which utilize a polycrystalline silicon floating gate and a polycrystalline silicon control gate separated by an SiO.sub.2 dielectric layer, such as the problems of sharp silicon points resulting from polysilicon grain growth causing low dielectric breakdown strength. In contrast to the prior art, a composite dielectric layer serves as a partially relaxable dielectric between the control gate and the floating gate of an EEPROM or an EPROM. The composite dielectric layer provides high capacitance between the floating gate and the control gate without the insulative and breakdown problems encountered with prior art thin dielectric layers. Electron injection takes place through the gate oxide between the drain extension or the floating gate (EEPROM), and between the channel and the floating gate (EPROM). In another embodiment of this invention, the composite dielectric layer is also implemented between the drain extension (EEPROM) or the channel (EPROM) and the floating gate and serves as the tunnel oxide.

REFERENCES:
patent: 4336603 (1982-06-01), Kotecha et al.
patent: 4432072 (1984-02-01), Chao et al.
patent: 4535349 (1985-08-01), Weinberg
Iizuka et al, "Electrically Alterable Avalanche-Injection-Type MOS Read-Only Memory with Stacked-Gate Structure," IEE Transactions on Electron Devices, vol. ED-23, No. 4, Apr. 1976, pp. 379-387.
DiMaria et al, "Electrically-Alterable Memory Using a Dual Electron Injector Structure," IEE Electron Device Letters, vol. ED-1, No. 9, Sep. 1980, pp. 179-181.
DiMaria et al, "Dual-Electron-Injector-Structure Electrically Alterable Read-Only-Memory Modeling Studies," IEEE Transactions on Electron Devices, vol. ED-28 (1981) Sep., No. 9, pp. 1047-1053.
Johnson et al, "A 16 Kb Electrically Erasable Nonvolatile Memory," IEEE International Solid State Circuits Conference, vol. 23, Feb. 1980, pp. 152-153, 271.

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