Partially-overlapped interconnect structure and method of...

Details Partially-overlapped interconnect structure and method of... Partially-overlapped interconnect structure and method of...

1998-02-20

2002-05-28

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S765000, C257S771000

Reexamination Certificate

active

06396151

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to an interconnect structure and more particularly, relates to an interconnect structure consisting of a contact and an interconnect line having an alloy film formed thereinbetween as an etch-stop during the interconnect line forming process.
BACKGROUND OF THE INVENTION
In modern VLSI and ULSI semiconductor devices, the dimensions of the devices are continuing to shrink. In order to allow more devices to be built on the same size real estate, the vertical dimension of the semiconductor devices has been increased. The increasing vertical dimension of the devices requires more levels of metal interconnection to be built in order to connect the various devices on a chip. These metal interconnections, for instance, include local interconnects or straps which electrically connect closely spaced devices. The technology for fabricating multiple levels of metal interconnects therefore has become more important.
The fabrication of a metal interconnect generally involves the blanket deposition of a metal conductive layer over the devices to be connected and then photomasking and etching the metal layer to form the interconnects. Both wet etching and reactive ion etching (RIE) techniques are used in etching the metal interconnects. The wet etching technique provides a desirable etch rate ratio (ERR) or a high selectivity for the metal not to be etched such that minimal damage is done to the underlying features on the chip. Since wet etching is isotopic in nature, the precise control of a submicron-level etching in high density integrated circuits is difficult. The reactive ion etching technique, on the other hand, is anisotropic in nature and therefore is more preferred in forming interconnects and studs in VLSI or ULSI devices. The RIE technique is more effective in controlling submicron dimensions on high density devices.
Referring initially to
FIG. 1
, where an enlarged, cross-sectional view of a conventional interconnect structure
10
of a semiconductor device is shown. The interconnect structure
10
is built on a silicon substrate
12
which has active regions
14
and
16
of either P or N type. The device is similar to a field-effect-transistor (FET) formed on a gate oxide insulation layer
22
on silicon substrate
12
. A first level contact studs
18
and
20
are formed on the active regions
14
and
16
in the thick oxide insulation layer
24
. The contact studs
18
and
20
connect the semiconductor device to first level metal lines
26
and
28
that are formed in a first level metalization layer (not shown). The contact studs
18
and
20
can be formed of tungsten with titanium or titanium/titanium nitride layers surrounding the studs. After the interconnect lines
26
and
28
are covered by a second thick oxide insulation layer
32
, contact holes are opened through a photolithography and an etching process to form second level contact studs
34
and
36
. After a planarization process is carried out to form a smooth surface
38
, second level interconnect lines (or plugs)
42
and
44
can be built onto the device.
A currently used interconnect structure such as that shown in
FIG. 1
can be formed by an aluminum-based metalization process consisting of titanium layers over and under, titanium nitride cap lines and tungsten studs. The illustrated interconnect structure has a number of disadvantages of which most notably is the low electromigration resistance of the Al lines adjacent to the tungsten studs. Since tungsten studs act as a complete barrier to copper and aluminum transport, this results in copper depletion in Al areas adjacent to the studs. The copper depletion in turn leads to an electromigration open failure in the Al. To avoid this problem, a set of down stream ground rules that are based on reliability data are required. These rules limit the performance of advanced CMOS logic chips.
A solution to this interconnect problem is therefore to replace the tungsten stud with a low resistivity material, such as aluminum, through which aluminum or copper can diffuse. An obvious problem in using aluminum studs is that during a subsequent etching step for forming the interconnect lines overlying the studs, a misalignment in the photomasking process may result in partially covered studs which during the etching process, can be etched away by the etchant used for etching the interconnect line. This creates voids in the aluminum studs and will possibly lead to the failure of the studs.
Others have attempted to solve the problem by proposing various solutions. For instance, U.S. Pat. No. 4,925,524 to Beatty discloses a method of using a chromium layer as an etch stop. The chromium layer is removed with an oxygen/chlorine plasma which has high selectivity to silicon oxide.
However, it is also known that chlorine is highly effective in etching away aluminum. U.S. Pat. No. 4,668,335 to Mockler, et al concerns an aluminum reactive ion etching technique that stops at a layer of titanium tungsten. The etch stop layer of titanium tungsten is then removed in a wet etching process. The method has the drawback that, for submicron dimensions in high density devices, lateral etching of titanium tungsten by a wet etch method can result in severe damage to the metal interconnect lines. U.S. Pat. No. 5,256,597 to Gambino et al. discloses the use of a self aligned conducting etch-stop for interconnect patterning. However, in this method, a sacrificial alloying layer must first be deposited on a conductive etch-stop layer before an interconnect layer can be deposited and thus requiring an extra processing step which is costly and time-consuming.
In a copending application Ser. No. 08/332,328 assigned to the common assignee of the present invention which is incorporated here in its entirety by reference, an interconnect structure for an integrated circuit for resisting electromigration when high current densities pass through the interlayer contact regions of the structure is disclosed. The structure includes interconnect lines formed of a metal of copper, copper alloys, aluminum or aluminum alloys over a via or stud formed of an aluminum-copper alloy. An aluminum-copper alloy is used in the stud in order to (1) avoid the etching away of the stud during an etching process for the interconnect lines overlying the stud when the stud is only partially covered by the line, (2) eliminate the highly resistive tungsten vias, and (3) allow for diffusion of aluminum and copper through the Al
2
Cu via (stud). It would be more desirable if aluminum can be used in the stud based on its lower resistivity characteristics.
It is therefore an object of the present invention to provide an interconnect structure for providing electrical communication between an interconnect and a contact that does not have the drawbacks and shortcomings of conventional interconnect structures.
It is another object of the present invention to provide an interconnect structure for providing electrical communication between an interconnect and a contact that allows a metal line to only partially overlap a metal stud during the fabrication process.
It is a further object of the present invention to provide an interconnect structure for providing electrical communication between an interconnect and a contact that can be fabricated by a self-aligning method in which an etch-stop layer is built on an aluminum stud.
It is another further object of the present invention to provide an interconnect structure for providing electrical communication between an interconnect and a contact wherein a complete overlap of the contact by the interconnect is not necessary.
It is yet another object of the present invention to provide an interconnect structure for providing electrical communication between an interconnect and a contact wherein an undesirable etching of the contact by an interconnect etching process can be avoided.
It is still another object of the present invention to provide an interconnect structure for providing electrical communication between an interconn

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