Partially enabled programmable logic device

Details Partially enabled programmable logic device Partially enabled programmable logic device

1987-09-08

1989-06-13

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307469, 364716, H03K 19177

Patent

active

048395390

ABSTRACT:
A programmable logic device include an AND gate array and an OR gate array, at least one of which is programmable by the user. The AND gate array includes a plurality of input lines, a plurality of product term lines which cross said plurality of input lines, and a plurality of programmable elements located at the intersections between the input and product term lines. An activation control circuit is also provided for activating at least one of the product term lines while keeping those product term lines which are not used for programming deactivated. With this structure, the waste of power can be minimized.

REFERENCES:
patent: 4032894 (1977-06-01), Williams
patent: 4567385 (1986-01-01), Falater et al.
patent: 4645953 (1987-02-01), Wong
patent: 4691123 (1987-09-01), Hashimoto
patent: 4761570 (1988-08-01), Williams
Flaker et al., "Programmed Power Proportioning for PLA's", IBM T.D.B., vol. 18, No. 4, Sep. 1975, pp. 1047-1048.

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