Partially decoded instruction cache

Details Partially decoded instruction cache Partially decoded instruction cache

1996-06-18

1997-09-16

Donaghue, Larry D.

395386, 395389, 395392, 395382, 395350, G06F 938

Patent

active

056690118

ABSTRACT:
A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions. A bit in each instruction cache entry indicates whether the instructions in the two slots are independent, so that they can be executed in parallel, or dependent, so that they must be executed sequentially. Using a single bit for this purpose allows two dependent instructions to be stored in the slots of the single cache entry.

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Bandyopadhyay et al. "Micro Code Based RISC Architecture" IEEE; 1987.
Hinton "80960--Next Generation" IEE 1989.
Clipper 32-Bit Micro Processor User's Manual pp. 2-1; 2-6--2-11.

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