Partially de-coupled core and periphery gate module process

Details Partially de-coupled core and periphery gate module process Partially de-coupled core and periphery gate module process

2003-07-14

2004-12-28

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Chemical etching

C438S669000, C438S587000, C438S585000, C438S275000, C438S258000

Reexamination Certificate

active

06835662

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to the manufacture of semiconductor devices and, more specifically, relates to the manufacturing of semiconductor devices by a partially de-coupled core and periphery gate module process.
BACKGROUND ART
In the semiconductor industry, manufacturers scale down the device dimensions to increase the performance as well as reduce the cost of manufacture. The scaling down of devices has led to the development of several new processing techniques. In the manufacture of certain devices, wet etching has been replaced with dry etching (plasma etching, reactive ion etching and ion milling). Low-resistivity suicides and refractory metals are used as replacements for high-resistivity polysilicon interconnections. Multiple-resists have been developed to compensate for wafer surface variations that thwart accurate fine-line lithography.
However, improved lithography processing techniques continue to be the main factor in the ability to scale devices. Improvements have come in, for example, lithographic tools, such as 1:1 optical projection systems fitted with deep-ultraviolet source and optics. Further, new photoresist materials have been introduced. Further still, new processes have been developed, such as a multilayer resist utilizing a top resist sensitized to X-ray or electron-beam and a bottom straight optical resist layer(s).
DISCLOSURE OF INVENTION
Despite the enhancements to lithographic tools, materials and processes, there exists a strong need in the art for an invention which forms a line and space pattern including at least two variable critical dimensions on a substrate sub-divided into regions. Further, there is a need for an invention that forms a line and space sub-pattern in one region that includes a first feature comprising a first critical dimension different than a second critical dimension of a second feature in another region of the substrate. Further, there is a need to form one of the features to include a critical dimension less than achievable at a resolution limit of lithography. Further still, there is a need to form one of the features to include a critical dimension achievable at a resolution limit of lithography. Additionally, there is a need for an invention that saves steps in a manufacturing process by reducing the number of steps used to form a mask used in the process. For example, a second mask layer used to form spacers in one region to reduce the lateral dimension in a hard mask may also be used to form spacers, e.g., transistor spacers, on the sidewalls of gates previously formed in another region. Additionally, there exists a need for an invention that forms gates and spaces comprising different critical dimensions in the at least two regions of the substrate that reduces the processing steps required to form the gates and spaces.
According to one aspect of the invention, the invention is a method of forming a layer comprising a line and space pattern over a substrate including a first region and a second region, the method comprising the steps of: depositing and patterning a first hard mask layer over the layer to form a master line and space pattern therein, wherein a first master line and space pattern in the hard mask layer includes at least one line and at least one space of a minimum dimension dictated by a resolution limit of lithography; etching the layer to form the line and space pattern in the second region corresponding to the first master line and space pattern in the hard mask layer in the second region, wherein a line in the second region includes a first critical dimension (B) achievable at the resolution limit of lithography; depositing a second hard mask layer over the patterned first hard mask layer, etching the second hard mask layer to form sidewall spacers on sidewalls of at the least one line in the hard mask layer in the first region, wherein the minimum dimension of the at least one space in the first hard mask layer in the first region is reduced to a second critical dimension (A) less than achievable at the resolution limit of lithography; to form sidewall spacers on sidewalls of the at least one line in the second region; and etching the layer to form the line and space pattern in the first region corresponding to the first master line and space pattern in the hard mask layer in the first region, wherein a space in the first region includes the second critical dimension (A) less than achievable by the resolution limit of lithography.
According to another aspect of the invention, the invention is a method of patterning a layer on a substrate including a first region and a second region, the method comprising the steps of: providing a substrate including the layer to be patterned interposed between the substrate and a first hard mask layer to be patterned; coating the first hard mask layer to be patterned with a first photosensitive layer; patterning and etching the first photosensitive layer to form a first patterned image including lines and at least one space, the lines in the first photosensitive layer and the at least one space include substantially vertical walls and include a minimum dimension (B) achievable at a resolution limit of lithography; transferring to the first hard mask layer the first patterned image by anisotropically etching the first hard mask layer to form lines and at least one space, the lines and the at least one space in the first hard mask layer include substantially vertical walls and the minimum dimension (B) achievable at the resolution limit of lithography; coating the first hard mask layer with a second photosensitive layer; patterning and etching the second photosensitive layer to form a second patterned image including a mask over the first region and exposing the second region; etching the layer in the second region to form a line and space pattern therein including at least one line in the second region including the critical dimension (B) achievable at the resolution limit of lithography; depositing a conformal hard mask layer over the hard mask layer, exposed surfaces of the layer and exposed surfaces of the substrate; forming sidewall spacers on the vertical walls of the lines of the first hard mask in the first region whereby the minimum dimension (B) of the at least one space in the first region is reduced; forming sidewall spacers on the vertical walls of the at least one line in the second region; coating the substrate with a third photosensitive layer; patterning and etching the third photosensitive layer to form a third patterned image, wherein the first region is exposed and a remaining portion of the third photosensitive layer acts as a mask in the second region; etching the layer in the first region to form a line and space pattern, wherein the at least one space in the layer in the first region includes a second critical dimension (A) less than achievable by the resolution limit of lithography.
According to another aspect of the invention, the invention is a semiconductor device, comprising: a semiconductor substrate including a first region, a second region and an active region; a dielectric layer formed over the semiconductor substrate; a conductive layer formed over the dielectric layer, wherein the conductive layer includes: a first pattern in the first region comprising lines and an opening, the opening includes a first critical dimension (A) less than achievable at a resolution limit of lithography, and a second pattern in the second region comprising at least one line including a second critical dimension (B) achievable at a resolution limit of lithography; and a sidewall spacer formed on a sidewall of the at least one line, the sidewall spacer being formed from a hard mask layer.


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U.S. Appl. No. 10/619,804;

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