Partial word to full word parallel data shifter

Details Partial word to full word parallel data shifter Partial word to full word parallel data shifter

1991-12-16

1993-03-09

Logan, Sharon D.

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

341141, H03M 700

Patent

active

051929503

ABSTRACT:
A partial word to full word parallel data shifter comprises 2N-1 multiplexer for selectively receiving data from the incoming current data word of width up to N, or from remainder bits of previously received data. The multiplexers output their data to 2N-1 latches, N of which output a full parallel data word and N-1 of which can recirculate up to N-1 remainder bits back to the multiplexers. If the number of remainder bits plus the number of data bits for the currently received word is less than N, the bits in the first N latches are not output but rather recirculate to the multiplexers where they are aligned for generating a full N bit output word with the most significant bit(s) of the next incoming parallel data.

REFERENCES:
patent: 4675652 (1987-06-01), Machado
patent: 5081654 (1992-01-01), Stephenson, Jr. et al.

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