Partial wafer bonding and dicing

Details Partial wafer bonding and dicing Partial wafer bonding and dicing

2006-07-18

2006-07-18

Baumeister, B. William (Department: 2891)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

With attachment to temporary support or carrier

C438S458000, C438S459000, C438S421000, C438S977000, C438S456000, C257SE21606

Reexamination Certificate

active

07078320

ABSTRACT:
Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.

REFERENCES:
patent: 4962879 (1990-10-01), Goesele et al.
patent: 5091331 (1992-02-01), Delgado et al.
patent: 5654226 (1997-08-01), Temple et al.
patent: 5668033 (1997-09-01), Ohara et al.
patent: 6004866 (1999-12-01), Nakano et al.
patent: 6010591 (2000-01-01), Gosele
patent: 6013534 (2000-01-01), Mountain
patent: 6538330 (2003-03-01), Forbes
patent: 6555901 (2003-04-01), Yoshihara et al.
patent: 6616854 (2003-09-01), Jones et al.
patent: WO9925019 (1999-05-01), None
K. Gann, “High Density Packaging of Flash Memory”, IEEE, 1998, pp. 96-98.
V. Dragoi et al., “Reversible Wafer Bonding For Reliable Compound Semiconductor Processing”, IEEE, 2002, pp. 331-334.
G. Reed, “Semiconductor Packaging”, Semiconductor International, Sep., 2003, pp. 50.

Affiliated with

Also associated with

Rating

Partial wafer bonding and dicing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Partial wafer bonding and dicing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partial wafer bonding and dicing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3583241