Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-12-22
2003-12-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189011, C365S230060
Reexamination Certificate
active
06661730
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory arrays, and particularly relates to those memory arrays incorporating passive element memory cells.
2. Description of the Related Art
Integrated circuits incorporating a memory array usually subdivide the array into a sometimes large number of sub-arrays. As used herein, a sub-array is a contiguous group of memory cells having contiguous word and bit lines generally unbroken by decoders, drivers, sense amplifiers, and input/output circuits. This is done for any of a variety of reasons. For example, the signal delays traversing down word lines and bit lines which arise from the resistance and the capacitance of such lines (i.e., the RC delays) may be very significant in a large array. These RC delays may be reduced by subdividing a larger array into a group of smaller sub-arrays so that the length of each word line and/or each bit line is reduced. As another example, the power associated with accessing a group of memory cells may dictate an upper limit to the number of memory cells which may be accessed simultaneously during a given memory cycle. Consequently, a large memory array is frequently subdivided into smaller sub-arrays to decrease the number of memory cells which are simultaneously accessed. As yet another example, in some memory technologies the memory array is divided into sub-arrays to ensure that some of the memory array is available for internal refresh operations.
With most memory technologies, the active or selected bits during a particular cycle tend to be very localized, frequently within a single sub-array which is selected during the particular cycle. In a dynamic memory device (e.g., a DRAM device) all of the memory cells along a selected word line are destructively accessed during an active cycle. Consequently, all of the memory cells read during a given cycle usually share the same word line in the same sub-array and are thus very localized. Since the memory cells are destructively read during the cycle, all of the memory cells to be written during a given cycle are usually written into memory cells along the same word line in the same sub-array. Those memory cells which are read during a read cycle traditionally are likewise all written (or at least available to be written) during a write cycle.
Many devices utilizing flash EEPROM technology include a large register which receives data from the external interface, and when a sufficiently large number of bits of data have been communicated to the device, the bits are written in pages into the main memory array of the device. It is essential to the cell simplification of flash EPROM technology to program and erase simultaneously to groups of memory cells that are all located in one sub-array of the memory since data is written from the page into such a cluster of cells and is read from this cluster of cells.
Lastly, as yet another example, Ferro-Electric memory devices also are organized to access all of the memory cells along a selected word line during both a read or a write cycle. Consequently, all of the bits read or written during a given cycle are traditionally clustered in one or a small number of sub-arrays.
Integrated circuits incorporating a passive element memory array require a high-voltage and high-current programming voltage source due to the large number of leakage paths in the array and the high voltage required to program the element conductivity. If provided on chip, the area required by such on-chip circuitry to generate the programming voltage source is substantial. It is not unusual to consume 10 to 30% of the chip area for such on-chip programming voltage sources (e.g., charge pumps). Since many types of passive element memory arrays are write once memory arrays, the read bandwidth is frequently of greater significance than the write bandwidth. There remains a need for improved architectures and methods of operation to decrease programming power without decreasing the read bandwidth of such memories.
SUMMARY OF THE INVENTION
Traditional memory architectures provide for selecting the same portion of the memory array irrespective of whether a read cycle or a write cycle is performed. Since the selected memory cells corresponding to the data being read or written during a given cycle are usually very tightly clustered, one (or possibly a small number) or sub-arrays are activated in a given cycle for both read and write cycles.
In accordance with the present invention, the bits read during a single read operation may be physically spread out into a large number of sub-arrays. All such sub-arrays are activated (or selected) during a read operation, but a smaller number of sub-arrays are activated during each of several write cycles. Consequently, the read bandwidth remains high and is driven by the number of bits read at the same time. But the write power is reduced since during each write cycle, a smaller number of bits are written. The present invention is particularly advantageous for use with a passive element memory array. The same programming voltage source may be shared by the various groups of sub-arrays during write cycles rather than requiring a large programming voltage source which would otherwise be necessary if simultaneously programming the same number of bits accessed during a read operation.
In one embodiment a passive element memory array includes many sub-arrays which are separately selectable in groups, each group containing one or more sub-arrays. A small number of the groups, preferably just one, are selected to write data simultaneously into the members of the group. Writing continues by cycling through many of the groups, preferably all of the groups, to complete writing all of the data in a set. To read the data set, all sub-arrays in the same many of the groups are simultaneously accessed. Such data is read therefore at a high data rate desirable for the user of the memory, while the write power is reduced because a smaller number of groups, preferably one, is simultaneously selected for writing.
In another embodiment of the present invention, less than all sub-arrays in the same many of the groups may be simultaneously accessed to read the data set, although a smaller number of groups are simultaneously selected for writing than are selected for reading data in a set.
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Crowley Matthew P.
Scheuerlein Roy E.
Elms Richard
Matrix Semiconductor Inc.
Nguyen Tuan T.
Zagorin O'Brien & Graham LLP
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