Partial scan testability utilizing reconvergence through sequent

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371 221, 39518306, 364488, 364489, H04B 1700

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active

055027300

ABSTRACT:
A method of selecting circuit elements in a sequential circuit for partial scan testing relies upon analyzing and breaking reconvergence through the selected circuit element. Different types of reconvergences present in the circuit and their affect on the circuit testability are considered. Harmful reconvergence present in the circuit are broken by scanning a memory element present in the reconvergence path.

REFERENCES:
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5132974 (1992-07-01), Rosales
patent: 5345393 (1994-09-01), Ueda
Chickermane et al., A Fault Oriented Partial Scan Design Approach, 1991, IEEE, pp. 400-403.
Chen et al., Single-Fault Fault Collapsing Analysis in Sequential Logic Circuits, 1990, pp. 809-814.
Erwin Trischler, "Incomplete Scan Path with an Automatic Test Generation Methodology", Proceedings of the International Test Conf. pp. 153-162, 1980.
M. Abramovici et al, "the Best Flip-Flops to Scan", Proceedings of the International Test Conf. pp. 166-173, 1991.
Prashant S. Parikh et al, "A Cost-Based Approach to Partial Scan", Proceedings of the 30th ACM/IEEE Design Automation Conf. pp. 225-259, 1993.
Cheng et al, "An Partial Scan Method for Sequential Circuits with Feedback", IEEE Transactions on Computers, vol. 34, pp. 544-548, Apr. 1990.
M. Abramovici et al, "Smart and Fast Test Generation for VLSI Scan Design Circuits", in IEEE Design and Test of Computers, vol. 3, pp. 43-54, Apr. 1986.

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