Partial response receiver with clock data recovery

Pulse or digital communications – Equalizers

Reexamination Certificate

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C375S371000

Reexamination Certificate

active

07433397

ABSTRACT:
In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second edge samples. The phase of the sampling clock signal is adjusted based, at least in part, on the first edge sample if the set of data samples matches a first data pattern and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

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