Partial product generating circuit

Details Partial product generating circuit Partial product generating circuit

1998-11-05

2000-05-23

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

327408, H03K 1762

Patent

active

060669780

ABSTRACT:
A group of pass transistors causes x.sub.i, x.sub.i-- B to pass therethrough when 1X indicates affirmation but not pass therethrough when 1X indicates negation, and causes x.sub.i-1, x.sub.i-1-- B to pass therethrough when 2X indicates affirmation but not pass therethrough when 2X indicates negation. In a switch-transistor arrangement portion, when each of 1X and 2X has a value indicating negation, a first electric potential appears at a first node, and a second electric potential appears at a second node. A positive-and-negative-responding pass-transistor group causes the value of the first node to pass therethrough when COMP has a value indicating negation, and causes the value of the second node to pass therethrough when COMP has a value indicating affirmation.

REFERENCES:
patent: 5760622 (1998-06-01), Ishigaki
patent: 5789966 (1998-08-01), Bechade
N. Ohkubo, et al., "A 4.4 ns CMOS 54 .times.54-b Multiplier Using Pass-Transistor Multiplexer", IEEE Journal of Solid-State Circuits, vol. 30, No. 3, Mar. 1995, pp. 251-256.
C.R. Baugh, et al., "A Two's Complement Parallel Array Multiplication Algorithm", IEEE Transactions of Computers, vol. C-22, No. 12, Dec. 1973, pp. 1045-1047.
L.P. Rubinfield, "A Proof of the Modified Booth's Algorithm for Mulitiplication", IEEE Transactions of Computers, Oct. 1975, pp. 1014-1015.
Sholmo Waser, Monolithic Memories, Ince, "High-Speed Monolithic Mulitpliers for Real-Time Digital Signal Processing," Oct. 1978, pp. 19-29.

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