Partial mismatch-shaping digital-to-analog converter

Details Partial mismatch-shaping digital-to-analog converter Partial mismatch-shaping digital-to-analog converter

2001-10-01

2004-02-24

Jeanglaude, Jean (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000

Reexamination Certificate

active

06697004

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital-to-analog converters (DACs), and more particularly to mismatch-shaping DACs.
2. Description of Related Art
Data converters, both digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), are ubiquitous in applications involving digital signal processing of real-world signals such as those found in communication systems, instrumentation, and audio and video processing systems. A class of data converters referred to as delta-sigma data converters are widely used in many such applications requiring mododerate to high precision, and having low to moderate signal bandwidths. Using well known techniques such as oversampling relative to the bandwidth of the signal to be converted, coarse internal quantization, and quantization noise-shaping, delta-sigma data converters perform high-precision data conversion functions in VLSI circuits that are optimized for digital circuitry. While coarse quantization is used to simplify analog processing within the data converter, oversampling and quantization noise-shaping techniques are used to achieve high precision data conversion despite errors introduced by the coarse quantization.
As is well known in the VLSI circuit design arts, owing to a high sensitivity to analog component mismatches and other circuit errors present in at least one of the internal DACs, non-linearity is introduced into the signal of interest. Unlike other noise sources, the non-linearity, which can be modeled as additive error and is referred to as “DAC noise”, is not attenuated by the processing chain and therefore directly degrades the overall signal-to-noise ratio (SNR) of the data converter. For example, and as described in more detail below with reference to the ADC
700
(of FIG.
7
), the output of a feedback DAC
712
is subtracted directly from the input signal (provided on input line
716
) via an adder
702
. Any error that is introduced by the feedback DAC
712
is directly added to the input signal. Any distortion introduced by the DAC
712
is regarded as an integral part of the input signal itself, as it possesses the same transfer function to the output. Therefore, the portion of this error within the passband of the decimation filter
714
directly degrades the overall conversion accuracy.
To overcome the non-linearity introduced by the mismatched components, until recently the majority of delta-sigma data converters were designed using internal one-bit DACs. While one-bit DACs effectively overcame the component mismatching problem, they force design tradeoffs to be made that, for a given oversampling level, significantly reduce the data conversion SNR below what is achievable using multi-bit quantization. With this in mind, various “mismatch-shaping” DAC architectures have been developed. These architectures use digital algorithms to perform spectral shaping of noise introduced by non-ideal analog circuit behavior. The algorithms require no specific knowledge of the particular analog errors introduced by the circuit. In these applications, digital signal processing (DSP) techniques are used to shape the errors such that most of their energy lies outside of the data converter signal band. Component mismatches are accepted as inevitable, but their negative effects are mitigated by the DSP techniques.
One prior art mismatch-shaping DAC architecture is described in a paper written by Dr. Ian Galton, entitled “Spectral Shaping of Circuit Errors in Digital-to-Analog Converters”, published in the IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 44, No.: 10, October 1997, referred to below as the Galton paper, and incorporated by reference in its entirety for its teachings on mismatch-shaping DACs. The DAC architectures described in this paper are also set forth in Dr. Galton's patent, U.S. Pat. No. 5,684,482, issued Nov. 4, 1997, also incorporated in its entirety herein for its teachings on mismatch-shaping DAC architectures. A DAC topology is described in both of the incorporated references that spectrally shapes the DAC noise caused by analog circuit component mismatches. As described in the incorporated U.S. patent, most of the mismatch-shaping DAC architectures generally take the form of the prior art DAC architecture
100
of FIG.
1
.
As shown in the
FIG. 1
, the prior-art mismatch-shaping DAC architecture
100
typically includes a digital encoder
5
and N one-bit DACs referred to as unit DAC-elements
6
. A digital input sequence x[n] is taken to be a sequence of non-negative integers less than or equal to N. Those of ordinary skill in the DAC design arts shall recognize that the digital input sequence can also comprise a signed representation. The sequence is provided as input to an input
9
of the digital encoder
5
. The digital encoder
5
maps each input sample to N outputs x
1
[n], x
2
[n], . . . x
N
[n]
10
such that the sum of the N outputs is equal to x[n]:
x
1
[n]+x
2
[n]+x
3
[n]+. . . +x
N
[n]=x[n]
  Equation 1
Each output bit x
i
[n] is provided as a corresponding input
12
to the unit DAC-elements
6
. The unit DAC-elements
6
operate to create N output signals y
1
[n], y
2
[n], y
N
[n] on respective outputs
16
. Each output signal y
r
[n] is then provided as an input to an adder
19
which sums the outputs to create an analog signal y[n] on an output
20
.
The digital encoder
5
sets x[n] of its N output bits to be high, and the remaining N−x[n] of its N output bits are set low. This enables 1-bit DACs
6
appropriately to convert the digital signal to a numerically equivalent analog output signal. If the 1-bit DACs
6
were to introduce no errors into their respective output signals, the output
20
y[n] of the DAC
100
would equal the input
9
, x[n], exactly. However, in practice, the errors are not zero because of the non-ideal circuit behavior described above. Non-ideal circuit behavior results in a gain error, a non-zero DC offset, and non-zero DAC noise.
The digital encoder
5
can be implemented in a variety of ways to select its output bits x
i
[n] and satisfy Equation 1 (above). Thus, the digital encoder
5
can modulate the DAC noise component of y[n] without affecting the signal component. The mismatch-shaping DACs perform this modulation such that the DAC noise is spectrally shaped in a manner that is similar to delta-sigma modulator quantization noise.
Another exemplary mismatch-shaping DAC topology
100
′ is described in the incorporated U.S. patent and shown in FIG.
2
. The number format used to represent the digital input value is unimportant as any convenient digital representation can be used. In the example shown in
FIG. 2
, the input bus
113
is 4-bits wide to accommodate the possibility of the number eight, represented by the binary number 1000
2
. The topology
100
′ is a special case of the topology
100
shown in FIG.
1
. As shown in FIG.
2
and described in more detail in the incorporated patent, the digital encoder
5
of
FIG. 1
is replaced with the digital logic
110
of FIG.
2
. The digital logic
110
of
FIG. 2
comprises three layers of digital devices called switching blocks
120
-
126
and labeled S
kr
, where k denotes a layer number and r denotes a position of the switching block
120
-
126
in its respective layer. Additionally, the topology
100
′ includes eight one-bit DACs
130
-
137
coupled to an adder
169
. A digital signal x[n] is input into the switching block
120
via an input bus
113
. The switching block
120
splits the input signal into two 3-bit output signals on outputs
140
and
141
. The signal on output
140
is fed to an input
142
of the switching block
121
, while the signal on output
141
is fed to an input
143
of the swi

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