Television – Image signal processing circuitry specific to television – Noise or undesired signal reduction
Reexamination Certificate
2001-01-05
2004-03-09
Kostak, Victor R. (Department: 2611)
Television
Image signal processing circuitry specific to television
Noise or undesired signal reduction
C375S234000
Reexamination Certificate
active
06704059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a channel equalizer for a digital television, and more particularly, to a partial fractionally spaced channel equalizer for a digital television which is capable of removing long and short ghosts.
2. Description of the Background Art
Generally, a channel equalizer compensates or equalizes a distortion generated when transmission signals pass multiple paths in a digital transmission system such as a high definition picture television. That is, the channel equalizer removed an interference noise generated in a digital television when a transmission channel is defective appears as a ghost phenomenon that images are overlapped on the digital TV screen.
FIG. 1
is a schematic block diagram of a tap spaced decision feedback equalizer (TS-DFE) in accordance with a conventional art.
As shown in the drawing, the TS-DFE includes feedforward filter unit
101
for receiving a sampling input signal (Si) of 10.76 MHz, a feedback filter unit
102
for receiving sliced output signals of a slicer which will be explained later, an adder
19
for adding tap signals outputted from the feedforward filter unit
101
and the feedback filter unit
102
and generating an equalizer output signal (Xi), a slicer
22
for receiving the equalizer output signal (Xi) and outputting a decision data (Di), a subtractor
21
for subtracting the equalizer output signal (Xi) from the decision data (Di) and outputting an error signal (Ei), and a multiplier
20
for multiplying the error signal (Ei) and a step size (s) to generate a step error signal (sEi) and outputting the step error signal (sEi) to the feedforward filter unit
101
and the feedback filter unit
102
.
The feedforward filter unit
101
includes a first delay array unit
11
having a plurality of delays (Z
−1
) for receiving and sequentially delaying the input signal (Si) sampled at a sampling speed of 10.76 Mz, a first multiplying unit
12
having multipliers for respectively multiplying the delay signals (Si-
1
, Si-
2
, . . . Si-
6
) outputted from the plurality of delays (Z
−1
) and the previous error signals (sEi-
1
), a first adding unit
13
for accumulating the multiplying result of each multiplier in the first multiplying unit
12
and outputting coefficients (C0, C1, C2, . . . C6), and a second multiplying unit
14
having a plurality of multipliers for respectively multiplying coefficients (C0, C1, C2, . . . , C6) and the input signal (Si) and outputting feedforward filter tap signals.
Like the feedforward filter unit
101
, the feedback filter unit
102
includes a second delay array unit
15
having a plurality of delays (Z
−1
) for receiving the decision data (Di) from the slicer
22
, sequentially delaying them, and outputting delay signals (Di-
1
, Di-
2
), a third multiplying unit
16
having multipliers for respectively multiplying the delay signals ((Di-
1
, Di-
2
) and the previous error signals (sEi-
1
), a second adding unit
17
for accumulating the multiplying result of each multiplier in the third multiplying unit
17
and outputting coefficients (C7 and C8), and a fourth multiplying unit
18
having a plurality of multipliers for respectively multiplying the coefficients (C7, C8) and the delay signals (Di-
1
, Di-
2
) and outputting feedback filter tap signals.
The operation of the conventional tap spaced decision feedback equalizer (TS-DFE) as described above will now be explained.
First, when the sampled input signal (Si) is inputted to the first delay array unit
11
of the feedforward filter unit
101
, the delays in the first delay array unit
11
as many as taps respectively delay the input signal and generate delay signals (Si-
1
, Si-
2
, . . . , Si-
6
). Each delayed signal (Si-
1
, Si-
2
, . . . Si-
6
) and the input signal (Si) are outputted to the first and the second multiplying units
12
and
14
.
At this time, the second multiplying unit
14
multiplies the input signal (Si) and the delayed signals (Si-
1
, Si-
2
, . . . Si-
6
) and the coefficients (C0, C1, . . . , C6) outputted from the first adding unit
13
to generate the feedforward filter tap signals, and outputs the feedforward filter tap signals to the adder
19
. Then, the adder
19
adds the feedforward filter tap signals to generate an equalizer output signal (Xi) and outputs the equalizer output signal (Xi) to the subtractor
21
and the slicer
22
.
Upon receipt of the equalizer output signal (Xi), the slicer
22
generates a decision data (Di) by using the equalizer output signal (Xi) and outputs it to the subtractor
21
and the second delay array unit
15
of the feedback filter unit
102
.
The subtractor
21
subtracts the decision data (Di) from the equalizer output signal (Xi) and generates the error signal (Ei) and outputs it to the multiplier
20
. Then, the multiplier
20
multipliers the error signal (Ei) by a predetermined step size (S) to generate a step error signal (sEi), and outputs the step error signal (sEi) to the first multiplying unit
12
of the feedforward filter unit
101
and the third multiplying unit
16
of the feedback filter unit
102
.
Like the operation of the feedforward filter unit
101
, the second delay array unit
15
of the feedback filter unit
102
receives the decision data (Di) from the slicer
22
, sequentially delays it to generate delayed signals (Di-
1
, Di-
2
), and outputs them to the third and the fourth multiplying units
16
and
18
. Then, the third multiplying unit
16
multiplies each delayed signal (Di-
1
, Di-
2
) and the previous error signals (sEi-
1
) outputted from the multiplier
20
, and outputs the multiplying result to the second adding unit
17
.
The second adding unit
17
accumulates the multiplying result to generate coefficients (C7, C8) and outputs them to the fourth multiplying unit
18
.
The fourth multiplying unit
18
multiplies the delayed signals (Di-
1
, Di-
2
) by the coefficients (C7, C8) to generate feedback filter tap signals, and outputs the feedback filter tap signals to the adder
19
, so that the feedback filter unit
102
is cooperatively operated with the feedforward filter unit
101
.
Accordingly, the TS-DFE of the conventional art equalizes the 10.76 MHz input signal by using the seven taps of the feedforward filter unit
101
and the two taps of the feedback filter unit
102
which receive and sequentially delay the input signal (Si). That is, the TS-DFE updates the coefficients and the operation of which will be explained as below in detail.
The function of the first and the second adding units
13
and
17
is expressed by the following equation (1).
C
(
n+
1)=
C
(
n
)+
s·Ei
(
n
)·
Xi
(
n
) (1)
Where C(n) and C(n+1) denotes coefficients at a symbol time (n) and a symbol time (n+1), 's' denotes a step size, Ei(n) denotes an error signal outputted from the subtractor
21
at a symbol time ‘n’, and Xi(n) denotes an equalizer output signal outputted from the adder
19
at the symbol time ‘n’. That is, the coefficient at the symbol time (n+1) can be expressed by the addition of the coefficient of the previous symbol time (n) and the value obtained by multiplying the equalizer output signal by the error signal having a predetermined step.
FIG. 2
is tap positions on a time axis of the TS-DFE of
FIG. 1
, which show a removable preghost and postghost range referenced to a main tap. That is, the TS-DFE of
FIG. 1
with 9 taps removes ghosts a from −3 T to 5 T Here, T is symbol time ({fraction (1/10.76)} MHz).
Accordingly, as for the TS-DFE of the conventional art, if the number of the taps is a lot in the filter unit, the distortion of a channel caused due to the long ghost at an external environment can be properly compensated, so that an interference between symbols can be easily removed.
However, with the conventional TS-DFE, a short ghost between symbols, for example, a reflection near the receiver by persons' motion, can not be removed. In addition, in case that a symbol time restoring circ
Kostak Victor R.
LG Electronics Inc.
LandOfFree
Partial fractionally spaced channel equalizer for digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Partial fractionally spaced channel equalizer for digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Partial fractionally spaced channel equalizer for digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3259418