Parity prediction circuitry for a multifunction register

Details Parity prediction circuitry for a multifunction register Parity prediction circuitry for a multifunction register

1979-09-10

1981-09-22

Malzahn, David H.

Excavating

364738, G06F 1110

Patent

active

042914078

ABSTRACT:
Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level "1" or logic level "0". This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.

REFERENCES:
patent: 3567916 (1971-03-01), Fullton, Jr.
patent: 3732407 (1973-05-01), Brewster et al.
patent: 3911261 (1974-09-01), Taylor

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