Parity prediction circuit for adder/counter

Details Parity prediction circuit for adder/counter Parity prediction circuit for adder/counter

1978-06-05

1980-09-23

Malzahn, David H.

Boots, shoes, and leggings

G06F 1110

Patent

active

042246806

ABSTRACT:
A parity prediction circuit for predicting parity in an adder, counter or similar device. The parity prediction is obtained with a parity prediction network connected from most significant bit to least significant bit. The parity prediction network is used in place of a parity generator or in combination with a parity generator for error checking purposes. In a special application, the parity prediction is employed for a ripple-carry type counter where the predicted parity bit is produced by a single network of NAND gates connected in series from high-order to low-order counter bits. The predicted parity is available no later than the completion of the carry-out propagation.

REFERENCES:
patent: 3141962 (1964-07-01), Sakalay
patent: 3287546 (1966-11-01), Geller
patent: 3732407 (1973-05-01), Brewster et al.
Kuckein, "High-Speed Parity Predictor for Adder", IBM Tech. Disclosure Bulletin, vol. 17, No. 2, Jul. 1974, pp. 540-542.

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