Parity predict network for M-level N'th power galois arithmetic

Details Parity predict network for M-level N'th power galois arithmetic Parity predict network for M-level N'th power galois arithmetic

1976-03-29

1977-07-12

Atkinson, Charles E.

Registers

Transfer mechanism

Traveling pawl

G06F 1110

Patent

active

040356264

ABSTRACT:
A parity predict circuit for an M-level N'th power Galois arithmetic gate using binary logic elements and a method of the designing thereof is disclosed. The method involves an algorithm that the logic designer utilizes to visually analyze the output of the arithmetic gate using a heuristic technique to determine the procedure for intercoupling the outputs of the gate's 1 through m-1 levels of parity trees as inputs to the parity predict parity tree. This visual analysis obviates the laborious mathematical treatment of the arithmetic gate priorly utilized to design a parity predict network.

REFERENCES:
patent: 3459927 (1969-08-01), Geller
patent: 3557356 (1971-01-01), Balza et al.
patent: 3649817 (1972-03-01), Keller et al.
patent: 3699323 (1972-10-01), Reinheimer
patent: 3805037 (1974-04-01), Ellison
patent: 3922536 (1975-11-01), Hampel et al.
Bodner, Parity Predict, IBM Technical Disclosure Bulletin, vol. 17, No. 7, Dec. 1974, pp. 2068-2072.

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