Parity generator circuit and method

Details Parity generator circuit and method Parity generator circuit and method

1988-02-17

1989-11-07

Smith, Jerry

Boots, shoes, and leggings

371 492, G06F 1110

Patent

active

048796751

ABSTRACT:
The parity generation circuit which is disclosed takes advantage of a property of the parity of a number before and after it has been incremented. This is characterized as the parity toggle property and it allows parity generation to be done on the most significant bits of an adder before the carry input to these most significant bits has been generated from the least significant bit portion of the sum produced by the adder. The final parity for the entire sum output of the addition process is adjusted quickly when the carry into the most significant bits of the sum becomes available from the least significant bit portion of the sum output. The parity toggle property of the invention allows for the quick adjustment of the parity without incurring the undue delay of waiting for the production of the carry output from the low order sum before commencing computations with the high order sum.

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S. A. Hallman, "Error Checking for a Full Carry Look-Ahead Adder," IBM TDB, Mar. 1985, pp. 6241-6248.
D. A. Shah, "100% Error Detection Scheme for Carry Save and Carry Look-Ahead Adders," IBM TDB, Feb. 1986, pp. 3736-3737.

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