Excavating
Patent
1982-03-08
1984-10-16
Atkinson, Charles E.
Excavating
307471, G06F 1110
Patent
active
044779046
ABSTRACT:
Each of the exclusive OR (XOR, or odd parity) and exclusive NOR (XNOR, or even parity) logical functions as between two signals input in both normal and inverted form is generated from separate logic circuits of two transfer gates implemented in complementary metal oxide semiconductor (CMOS) very large scale integrated circuit (VLSIC) technology. Replications of paired such XOR and XNOR logical circuits within a parity tree allow parity generation/detection as between 2.sup.N signals input in both normal and inverted form in only N propagation stages of typically average 0.9 nanosecond delay each stage when implemented in 11/4 micron feature size CMOS VLSIC.
REFERENCES:
patent: 4041326 (1977-08-01), Robinson
patent: 4424460 (1984-01-01), Bertelson
Atkinson Charles E.
Fuess William C.
Grace Kenneth T.
Sperry Corporation
Truex Marshall M.
LandOfFree
Parity generation/detection logic circuit from transfer gates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Parity generation/detection logic circuit from transfer gates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Parity generation/detection logic circuit from transfer gates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1948604