Parity-error injection system for an instruction processor

Details Parity-error injection system for an instruction processor Parity-error injection system for an instruction processor

1996-12-27

1999-02-16

Palys, Joseph

39518215, 395568, G06F 1100

Patent

active

058729100

ABSTRACT:
A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.

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